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21. 发明申请

US20090101978A1 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：US20090101978A1
公开(公告)日：2009-04-23
申请号：US11873521
申请日：2007-10-17
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的设计结构的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

22. 发明授权

US07517806B2 Integrated circuit having pairs of parallel complementary FinFETs 失效
标题翻译：具有成对的并联互补FinFET的集成电路
公开(公告)号：US07517806B2
公开(公告)日：2009-04-14
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
发明人： Andres Bryant , William F. Clark, Jr. , David M. Fried , Mark D. Jaffe , Edward J. Nowak , John J. Pekarik , Christopher S. Putnam
IPC分类号： H01L21/302
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

23. 发明申请

US20090020806A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20090020806A1
公开(公告)日：2009-01-22
申请号：US11778185
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L29/76
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定电容值）。

24. 发明授权

US07259590B1 Driver for multi-voltage island/core architecture 失效
标题翻译：多电压岛/核心架构驱动
公开(公告)号：US07259590B1
公开(公告)日：2007-08-21
申请号：US11276169
申请日：2006-02-16
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H03K19/0185
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.
摘要翻译：提供了一种用于为集成电路芯片的多电压岛/核心架构提供驱动器的系统和方法。互补金属氧化物半导体（CMOS）逆变器由高阈值电压p沟道场效应晶体管（hi-Vt PFET）和规则阈值电压n沟道场效应晶体管（NFET）构成，其使用最大正值电源（Vdd）在芯片上。基于最大Vdd，驱动CMOS反相器的电压岛/芯的Vdd和hi-Vt PFET的亚阈值泄漏电流要求来确定hi-Vt PFET的阈值电压。

25. 发明授权

US07187042B2 Backgated FinFET having different oxide thicknesses 失效
标题翻译：背衬FinFET具有不同的氧化物厚度
公开(公告)号：US07187042B2
公开(公告)日：2007-03-06
申请号：US11365504
申请日：2006-03-02
申请人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
发明人： Andres Bryant , Omer H. Dokumaci , Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/42368 , H01L29/42384 , H01L29/66795 , H01L29/7856
摘要： A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.
摘要翻译：在前栅侧和后栅极侧制造具有不同介电层厚度的背景FinFET的方法包括将杂质引入FinFET的鳍的至少一侧的步骤，以形成不同厚度的电介质层。可以通过注入引入的杂质增强或延迟电介质形成。

26. 发明授权

US07087966B1 Double-Gate FETs (field effect transistors) 有权
标题翻译：双栅FET（场效应晶体管）
公开(公告)号：US07087966B1
公开(公告)日：2006-08-08
申请号：US10908583
申请日：2005-05-18
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L31/0392
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括设置在第一和第二源极/漏极（S / D）区域之间的多个鳍片区域。该结构还包括多个前门和后门，每个前门和后门夹在两个相邻鳍片区域之间，使得前门和后门交替（即，一个前门，然后一个后门，然后一个前门，等等）。前门的宽度大于后门的宽度。前门和S / D区之间的电容小于后门和S / D区之间的电容。前门和S / D区之间的距离大于后门和S / D区之间的距离。

27. 发明授权

US07009265B2 Low capacitance FET for operation at subthreshold voltages 有权
标题翻译：低电容FET，用于在亚阈值电压下工作
公开(公告)号：US07009265B2
公开(公告)日：2006-03-07
申请号：US10710007
申请日：2004-06-11
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7833 , H01L29/1045 , H01L29/66537 , H01L29/6656 , H01L29/66583 , H01L29/7835 , H01L29/785
摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.
摘要翻译：场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。下层区域减少重叠电容，从而提高开关速度。欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

28. 发明授权

US06239591B1 Method and apparatus for monitoring SOI hysterises effects 失效
标题翻译：监测SOI隔音效应的方法和装置
公开(公告)号：US06239591B1
公开(公告)日：2001-05-29
申请号：US09303358
申请日：1999-04-29
申请人： Andres Bryant , Edward J. Nowak , Minh Ho Tong
发明人： Andres Bryant , Edward J. Nowak , Minh Ho Tong
IPC分类号： G01R1955
CPC分类号： H01L22/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for measuring hysteresis effects of a wafer process. The method comprises steps of generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.
摘要翻译：一种用于测量晶圆工艺的滞后效应的系统和方法。该方法包括以下步骤：产生具有等于延迟链的转变的延迟的脉冲宽度的脉冲，其中延迟链处于静态条件下相当长的时间; 对在环状振荡器已经在稳态条件下操作的脉冲宽度期间产生的环形振荡器进行计数; 将振荡次数与期望值进行比较; 并且将由比较步骤产生的差与由晶片工艺影响的滞后水平相关联。

29. 发明授权

US6159807A Self-aligned dynamic threshold CMOS device 失效
标题翻译：自对准动态阈值CMOS器件
公开(公告)号：US6159807A
公开(公告)日：2000-12-12
申请号：US157691
申请日：1998-09-21
申请人： Andres Bryant , Edward J. Nowak
发明人： Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A method of making a self-aligned dynamic threshold field effect device having a dynamic threshold voltage includes depositing a mandrel layer on the surface of an SOI substrate, then etching a gate opening in the mandrel layer. The gate opening is narrowed by depositing spacer material and a highly doped region, forming a low resistance body region, is created by ion implantation. The narrowed gate opening prevents the low resistance body from connecting the source/drain regions to be formed on opposite sides of the gate structure. A gate is formed by depositing a dielectric layer in the gate opening, and adding a layer of gate material, then chemical-mechanical polishing to the level of the mandrel layer, then removing the mandrel layer. Conventional processing is then used to create source/drain diffusion regions. The gate is connected to the body by creating a contact region at one end of the gate. The invention includes the device made by the method. The device needs less surface area than previous devices of this type due to the low resistance body and the connection region located at one end of the gate structure, and the method self-aligns the gate and the body region, while accurately controlling their relative sizes.
摘要翻译：制造具有动态阈值电压的自对准动态阈值场效应器件的方法包括在SOI衬底的表面上沉积心轴层，然后蚀刻心轴层中的栅极开口。栅极开口通过沉积间隔材料而变窄，并且通过离子注入产生形成低电阻体区域的高掺杂区域。狭窄的门开口防止低阻体连接要形成在栅极结构的相对侧上的源极/漏极区域。通过在栅极开口中沉积电介质层形成栅极，并且在栅极层上添加栅极材料层，然后进行化学机械抛光，然后除去芯棒层。然后使用常规处理来产生源极/漏极扩散区域。门通过在门的一端产生接触区域连接到身体。本发明包括通过该方法制造的装置。由于低电阻体和位于栅极结构一端的连接区域，该装置比之前的这种装置需要较少的表面积，并且该方法可自动对准栅极和体区，同时精确地控制它们的相对尺寸。

30. 发明授权

US6100564A SOI pass-gate disturb solution 有权
公开(公告)号：US6100564A
公开(公告)日：2000-08-08
申请号：US163950
申请日：1998-09-30
申请人： Andres Bryant , Edward J. Nowak , Minh H. Tong
发明人： Andres Bryant , Edward J. Nowak , Minh H. Tong
IPC分类号： H01L21/335 , H01L21/84 , H01L27/02 , H01L27/12 , H01L27/01 , H01L29/10
CPC分类号： H01L27/0288 , H01L21/84 , H01L27/1203 , H01L2924/0002
摘要： An SOI pass-gate disturb solution for an N-type MOSFET wherein a resistor is connected between the gate and the body of the FET to eliminate the disturb condition. The FET is fabricated in a substrate having a source, a drain and a gate, wherein the body of the field effect transistor is electrically floating and the transistor is substantially electrically isolated from the substrate. A high resistance path is provided coupling the electrically floating body of the FET to the gate, such that the body discharges to a low state before significant thermal charging can occur when the gate is low, and thus prevents the accumulation of a charge on the body when the transistor is off. The resistance of the high resistance path is preferably approximately 10.sup.10 Ohms-um divided by the width of the pass-gate.

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