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21. 发明授权

US06894330B2 Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor 失效
标题翻译：用于从铁电晶体管中读取状态并存储状态的存储器配置和方法
公开(公告)号：US06894330B2
公开(公告)日：2005-05-17
申请号：US09783187
申请日：2001-02-14
申请人： Harald Bachhofer , Georg Braun , Thomas Peter Haneder , Wolfgang Hönlein , Marc Ullmann
发明人： Harald Bachhofer , Georg Braun , Thomas Peter Haneder , Wolfgang Hönlein , Marc Ullmann
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C11/22
摘要： The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.
摘要翻译：读取或存储存储单元中的铁电晶体管的状态，并且在读取或存储期间在存储矩阵中的另外的存储单元中的另外的铁电晶体管的阈值电压增加或永久地增加。还提供了包括铁电存储单元的存储器配置。

22. 发明授权

US06697279B2 Ferroelectric read/write memory with series-connected memory cells (CFRAM) 失效
标题翻译：具有串联存储单元（CFRAM）的铁电读/写存储器
公开(公告)号：US06697279B2
公开(公告)日：2004-02-24
申请号：US09758300
申请日：2001-01-10
申请人： Ronny Schneider , Georg Braun
发明人： Ronny Schneider , Georg Braun
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： The memory device has series-connected ferroelectric memory cells in which a series circuit composed of a resistor and/or of a transistor for the ferroelectric capacitor of a respective memory cell is present. As a result, without unacceptably increasing the access time, the interference pulses at the ferroelectric capacitors of the memory cells which are not being addressed at that particular time and which are generated by the reading out or writing of the addressed memory cell are reduced in such a way that they have virtually no further influence on the non-addressed memory cells.
摘要翻译：存储器件具有串联连接的铁电存储器单元，其中存在由相应存储单元的铁电电容器的电阻器和/或晶体管组成的串联电路。结果是，在没有不可接受地增加访问时间的情况下，在特定时间没有被寻址并且通过寻址的存储器单元的读出或写入而产生的存储单元的铁电电容器处的干扰脉冲被减少它们对于非寻址存储器单元几乎没有进一步的影响。

23. 发明授权

US06500677B2 Method for fabricating a ferroelectric memory configuration 失效
标题翻译：铁电存储器配置的制造方法
公开(公告)号：US06500677B2
公开(公告)日：2002-12-31
申请号：US10027106
申请日：2001-12-26
申请人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
发明人： Renate Bergmann , Christine Dehm , Thomas Roehr , Georg Braun , Heinz Hoenigschmid , Günther Schindler
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.
摘要翻译：本发明提供了一种方法。在制造铁电存储器结构的方法的第一步骤中，提供了具有多个存储单元的衬底。每个存储单元具有至少一个选择晶体管，至少一个短路晶体管和至少一个铁电电容器。晶体管以导电方式连接到铁电电容器的第一电极。在下一步骤中，施加至少一个电绝缘层。在下一步骤中，产生用于连接铁电电容器的第二电极的至少一个接触孔。接下来，制造用于连接短路晶体管的接触孔。接下来，接触孔填充有导电材料。接下来，施加导电层并图案化，使得强电介质电容器的第二电极分别与短路晶体管导通。

24. 发明授权

US06487128B2 Integrated memory having memory cells and reference cells, and operating method for such a memory 有权
标题翻译：具有存储单元和参考单元的集成存储器以及用于这种存储器的操作方法
公开(公告)号：US06487128B2
公开(公告)日：2002-11-26
申请号：US09962411
申请日：2001-09-24
申请人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
发明人： Thomas Böhm , Heinz Hönigschmid , Thomas Röhr , Georg Braun , Zoltan Manyoki
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/14
摘要： The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.
摘要翻译：存储器具有相同构造的存储器单元和参考单元。通过经由第一开关元件将读取放大器的参考单元解耦，并且经由第二开关元件将连接到参考单元的位线的一部分电连接到电位线，将参考信息项写入参考单元携带参考信息。

25. 发明授权

US06452852B2 Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration 有权
标题翻译：具有刷新逻辑电路的半导体存储器配置和刷新半导体存储器配置的存储器内容的方法
公开(公告)号：US06452852B2
公开(公告)日：2002-09-17
申请号：US09767380
申请日：2001-01-22
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Thomas Röhr
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C11/406
摘要： In a semiconductor memory configuration, a refresh operation is always started by a refresh logic circuit when a comparison circuit determines that there is a specific minimum difference when comparing a characteristic variable of at least one reference memory cell with a reference value (VREF).
摘要翻译：在半导体存储器配置中，当比较电路确定在将至少一个参考存储单元的特征变量与参考值（VREF）进行比较时确定存在特定最小差异时，刷新逻辑电路总是开始刷新操作。

26. 发明授权

US06351422B2 Integrated memory having a differential sense amplifier 有权
标题翻译：具有差分读出放大器的集成存储器
公开(公告)号：US06351422B2
公开(公告)日：2002-02-26
申请号：US09820235
申请日：2001-03-28
申请人： Thomas Röhr , Thomas Böhm , Heinz Hönigschmid , Georg Braun
发明人： Thomas Röhr , Thomas Böhm , Heinz Hönigschmid , Georg Braun
IPC分类号： G11C700
CPC分类号： G11C11/22 , G11C7/12 , G11C7/22
摘要： The memory has writable memory cells. In addition, it has a bit line pair which connects the memory cells MC to a differential sense amplifier. A control unit is used for precharging the bit lines in a plurality of steps before one of the memory cells is conductively connected to one of the bit lines for a read access operation. For a write access operation, the control unit carries out no more than some of the bit line precharging steps provided for a read access operation before the sense amplifier transfers data to the bit line pair.
摘要翻译：内存有可写存储单元。此外，它具有将存储单元MC连接到差分读出放大器的位线对。控制单元用于在存储器单元之一导通地连接到用于读访问操作的位线之一之前的多个步骤中对位线进行预充电。对于写访问操作，在读出放大器将数据传送到位线对之前，控制单元执行不超过为读访问操作提供的一些位线预充电步骤。

27. 发明授权

US6157561A Integrated circuit memory with low resistance, segmented power supply lines 有权
标题翻译：具有低电阻，分段电源线的集成电路存储器
公开(公告)号：US6157561A
公开(公告)日：2000-12-05
申请号：US513587
申请日：2000-02-25
申请人： Tobias Schlager , Georg Braun , Heinz Hoenigschmid , Thomas Boehm
发明人： Tobias Schlager , Georg Braun , Heinz Hoenigschmid , Thomas Boehm
IPC分类号： G11C5/06 , H01L21/8242
CPC分类号： H01L27/10882 , G11C5/063
摘要： An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.
摘要翻译：一种集成存储器，其具有在其中延伸的并行导体轨迹的第一布线平面。存储器中的第二布线平面具有平行于导体轨迹的线段。字线各自由第一类型的导体轨道和与该导体轨道平行配置的段形成。第二类型的导体轨道连接到第一电源线以及配置在电池阵列内的第三布线平面中的区域。

28. 发明授权

US6137712A Ferroelectric memory configuration 有权
标题翻译：铁电存储器配置
公开(公告)号：US6137712A
公开(公告)日：2000-10-24
申请号：US440818
申请日：1999-11-15
申请人： Thomas Rohr , Heinz Honigschmid , Georg Braun
发明人： Thomas Rohr , Heinz Honigschmid , Georg Braun
IPC分类号： G11C14/00 , G11C11/22
CPC分类号： G11C11/22
摘要： The invention relates to a memory configuration comprising a multiplicity of memory cells. Each of the memory cells has at least one ferroelectric storage capacitor and a selection transistor. The memory cells are addressed via word lines and bit line pairs. It is possible for a reference signal obtained from a reference cell pair via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier. The sense amplifier is thereby assigned two bit line pairs connected in such a way that the reference signal is applied via the first bit line pair and, at the same time, the read signal is applied via the second bit line pair to the sense amplifier.
摘要翻译：本发明涉及包括多个存储单元的存储器配置。每个存储单元具有至少一个铁电存储电容器和选择晶体管。存储单元通过字线和位线对寻址。可以将从参考单元对经由位线对获得的参考信号与来自读出放大器中的存储单元的读取信号进行比较。因此，读出放大器被分配两个位线对，其连接方式是经由第一位线对施加参考信号，并且同时经由第二位线对将读取信号施加到读出放大器。

29. 发明授权

US08161219B2 Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed 有权
标题翻译：用于具有单独布置的总线线路的部分的存储器模块的分布式命令和地址总线架构
公开(公告)号：US08161219B2
公开(公告)日：2012-04-17
申请号：US12328690
申请日：2008-12-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G06F13/00
CPC分类号： G06F13/409
摘要： Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.
摘要翻译：描述了内存模块和电路板的分布式命令和地址总线架构。在一个实施例中，存储器模块包括设置在电路板边缘上的多个连接器引脚，所述多个连接器引脚包括耦合到多个数据总线的第一引脚，耦合到多个命令和地址总线的第二引脚线，其中第二引脚设置在第一和第二区域中，其中第一引脚的一部分设置在第一和第二区域之间。

30. 发明授权

US07936201B2 Apparatus and method for providing a signal for transmission via a signal line 有权
标题翻译：用于提供用于经由信号线传输的信号的装置和方法
公开(公告)号：US07936201B2
公开(公告)日：2011-05-03
申请号：US11644998
申请日：2006-12-22
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F5/06
CPC分类号： G06F13/1668
摘要： An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.
摘要翻译：一种用于经由信号线提供用于传输的信号的装置包括控制器电路，其具有用于指示信号线是否将处于非活动状态的信号的输出和耦合到控制器电路的开关电路，并且具有耦合到信号线。如果信号指示信号线处于非活动状态，则输出在不同的信号电平之间切换。

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