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21. 发明申请

WO2009003129A2 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION AND CHANNEL CHARACTERIZATION USING LIVE DATA 审中-公开
标题翻译：使用实时数据的自适应均衡和通道特征的方法和电路
公开(公告)号：WO2009003129A2
公开(公告)日：2008-12-31
申请号：PCT/US2008/068409
申请日：2008-06-26
申请人： RAMBUS INC. , LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
发明人： LEE, Hae-Chang , REN, Jihong , LEIBOWITZ, Brian S. , MADDEN, Christopher J. , LIN, Qi , ZERBE, Jared L.
IPC分类号： H04L25/02 , H04L25/03 , H04L1/20
CPC分类号： H04L25/03878 , H04L1/203 , H04L1/205 , H04L25/0224 , H04L25/0242 , H04L25/0264 , H04L25/0272 , H04L25/03012 , H04L25/03343
摘要： A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
摘要翻译：通信系统支持在相应的发射和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。另一个实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析比特误差以测量信道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

22. 发明申请

WO2007024446A2 LINEAR TRANSFORMATION CIRCUITS 审中-公开
标题翻译：线性变换电路
公开(公告)号：WO2007024446A2
公开(公告)日：2007-03-01
申请号：PCT/US2006/030411
申请日：2006-08-02
申请人： RAMBUS INC. , AMIRKHANY, Amir , STOJANOVIC, Vladimir, M. , ALON, Elad , ZERBE, Jared, L. , HOROWITZ, Mark, A.
发明人： AMIRKHANY, Amir , STOJANOVIC, Vladimir, M. , ALON, Elad , ZERBE, Jared, L. , HOROWITZ, Mark, A.
IPC分类号： G06F17/14
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译：变换电路包括第一电路和第二电路。第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。

23. 发明申请

WO2003032652A3 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 审中-公开
公开(公告)号：WO2003032652A3
公开(公告)日：2003-04-17
申请号：PCT/US2002/032602
申请日：2002-10-11
申请人： RAMBUS INC. , ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
发明人： ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
IPC分类号： G01R31/28
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit (101) circuit of the system and is transmitted to a receive (103) circuit. A similar pattern of information is generated in the receive (103) circuit and used as a reference. The receive (103) circuit compares the patterns. Any differences (114) between the patterns are observable. In one embodiment, a linear feedback shift (105, 108) register (LFSR) implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

24. 发明申请

WO2003032652A2 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 审中-公开
标题翻译：用于评估和优化信号系统的方法和装置
公开(公告)号：WO2003032652A2
公开(公告)日：2003-04-17
申请号：PCT/US2002/032602
申请日：2002-10-11
申请人： RAMBUS INC. , ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
发明人： ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
IPC分类号： H04Q
CPC分类号： G01R31/31717 , G01R31/31703 , G01R31/3183 , G06F11/221 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. Evaluation is accomplished using the same circuits actually involved in normal operation of the signaling system. Capability for in-situ testing of a signaling system is provided, and information may be obtained from the actual perspective of a receive circuit in the system. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. Preferably, the patterns are repeating patterns that allow many iterations of testing to be performed. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. Information obtained from testing may be used to assess the effects of various system parameters, including but not limited to output current, crosstalk cancellation coefficients, and self-equalization coefficients, and system parameters may be adjusted to optimize system performance. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
摘要翻译：描述了用于评估和优化信令系统的方法和装置。使用与信号系统的正常操作实际相关的相同电路进行评估。提供了对信号系统的原位测试的能力，并且可以从系统中的接收电路的实际角度获得信息。在系统的发送电路中产生测试信息的模式，并将其发送到接收电路。在接收电路中产生类似的信息模式并用作参考。接收电路比较图案。模式之间的任何差异是可观察的。优选地，图案是允许执行许多测试迭代的重复图案。在一个实施例中，实现线性反馈移位寄存器（LFSR）以产生模式。从测试获得的信息可以用于评估各种系统参数的影响，包括但不限于输出电流，串扰消除系数和自平衡系数，并且可以调整系统参数以优化系统性能。本发明的一个实施例可以用各种类型的信令系统来实现，包括具有单端信号和具有差分信号的信号系统。本发明的实施例可以应用于在给定时间在单个导体上传送单个信息位的系统和同时在单个导体上传送多个信息位的系统。

25. 发明申请

WO0221782A2 METHOD AND APPARATUS FOR CALIBRATING A MULTI-LEVEL CURRENT MODE DRIVER AND FOR GENERATING A MULTI-LEVEL REFERENCE VOLTAGE IN SYSTEMS USING EQUALIZATION OR CROSSTALK CANCELLATION 审中-公开
标题翻译：用于校准多级电流模式驱动器的方法和装置，以及使用均衡或CROSSTALK取消在系统中产生多级参考电压
公开(公告)号：WO0221782A2
公开(公告)日：2002-03-14
申请号：PCT/US0127478
申请日：2001-09-05
申请人： RAMBUS INC , WERNER CARL , HOROWITZ MARK , CHAU PARK , BEST SCOTT , LIAW H J , SIDIROPOULOS STEFANOS , ZERBE JARED LEVAN , KIM JUN
发明人： WERNER CARL , HOROWITZ MARK , CHAU PARK , BEST SCOTT , LIAW H J , SIDIROPOULOS STEFANOS , ZERBE JARED LEVAN , KIM JUN
IPC分类号： H04L25/02 , H04L25/03 , H04L25/08 , H04L25/49
CPC分类号： H04L25/0282 , H04L25/0272 , H04L25/0298 , H04L25/03878 , H04L25/08 , H04L25/4902
摘要： The current controller includes a multi-level voltage reference and receives at least onesource calibration signal. A comparator is coupled by a coupling network t the multi-level voltage reference and the source calibration signal. A selected voltage is applied from the multi-level voltage reference and a selected source calibration signal is applied to the comparator. Further, system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver. Further, low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation along a signal transmission line, crosstalk between adjacent lines, and signal reflections due to impedance discontinuities along the line.
摘要翻译：电流控制器包括多电平电压基准并且接收至少一个源校准信号。比较器通过耦合网络耦合多电平电压基准和源校准信号。从多电平参考电压施加所选择的电压，并且将选择的源校准信号施加到比较器。此外，示出了在总线系统中产生至少一个参考电压电平的系统和方法。电流驱动器上的参考电压发生器包括至少一个参考电压电平，至少一个控制信号和有源器件。有源器件耦合到至少一个控制信号，例如电流信号，以及所选择的至少一个参考电压电平的参考电压。有源器件被布置为基于在当前驱动器上采用的至少一个电流控制信号（例如均衡信号，串扰信号或其组合）来移位至少一个参考电压电平。此外，公开了用于多PAM通信系统的低延迟均衡机制，其减少信号校正机制中的延迟和复杂性。均衡机制分为用于多PAM信号驱动器的输入信号，并且补偿沿着信号传输线的衰减，相邻线之间的串扰以及由于沿线的阻抗不连续性引起的信号反射。

26. 发明申请

WO2012064537A3 USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE 审中-公开
标题翻译：使用时钟信号来减少自感电压噪声
公开(公告)号：WO2012064537A3
公开(公告)日：2012-07-12
申请号：PCT/US2011058525
申请日：2011-10-31
申请人： RAMBUS INC , LEIBOWITZ BRIAN S , ZERBE JARED L
发明人： LEIBOWITZ BRIAN S , ZERBE JARED L
IPC分类号： G06F1/04 , G06F1/32 , H03K19/0175
CPC分类号： G06F1/12 , G06F1/08 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In some embodiments, the modified timing signal is generated by skipping a pattern of clock transitions in the normal timing signal.
摘要翻译：所公开的实施例涉及使用修改的时序信号来减少同步系统中的自感应电压噪声的技术。在与同步系统中的确定性事件相关联的过渡时段期间，该技术使用基于正常定时信号生成的修改定时信号作为同步系统的定时信号。在瞬态时段之外，该技术使用正常时序作为同步系统的时序信号。在一些实施例中，通过跳过正常定时信号中的时钟转变的模式来生成修改的定时信号。

27. 发明申请

WO2012074689A1 CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES 审中-公开
标题翻译：用于与存储器件排序进行定时通信的时钟生成器
公开(公告)号：WO2012074689A1
公开(公告)日：2012-06-07
申请号：PCT/US2011/059851
申请日：2011-11-09
申请人： RAMBUS INC. , ZERBE, Jared L. , SHAEFFER, Ian P. , EBLE, John
发明人： ZERBE, Jared L. , SHAEFFER, Ian P. , EBLE, John
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G06F13/1689 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F13/161 , G06F13/1657 , G11C7/04 , G11C7/222 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
摘要翻译：存储器控制器包括时钟发生器，用于产生第一时钟信号和定时电路，以从第一时钟信号产生第二时钟信号。第二时钟信号与相应等级中的多个存储器件中的任何一个存储器件进行通信，包括第一等级中的第一存储器件和第二等级的第二存储器件。定时电路被配置为基于与第二存储器设备相关联的校准数据和与来自至少第一存储器的反馈相关联的定时调整数据来调整存储器控制器与第二存储器件通信时的第一时钟信号的相位设备。

28. 发明申请

WO2012021380A3 FAST-WAKE MEMORY 审中-公开
公开(公告)号：WO2012021380A3
公开(公告)日：2012-02-16
申请号：PCT/US2011/046669
申请日：2011-08-04
申请人： RAMBUS INC. , WARE, Frederick, A. , ZERBE, Jared, L. , LEIBOWITZ, Brian, S.
发明人： WARE, Frederick, A. , ZERBE, Jared, L. , LEIBOWITZ, Brian, S.
IPC分类号： G11C7/22 , G11C7/10 , G06F13/16 , G06F12/00
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.

29. 发明申请

WO2011041060A3 METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE IN PROGRAMMABLE DELAY LINES 审中-公开
标题翻译：用于降低可编程延迟线中的供应和终端噪声的方法和系统
公开(公告)号：WO2011041060A3
公开(公告)日：2011-07-14
申请号：PCT/US2010047282
申请日：2010-08-31
申请人： RAMBUS INC , SATARZADEH PATRICK , ZERBE JARED , DALY BARRY
发明人： SATARZADEH PATRICK , ZERBE JARED , DALY BARRY
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H03H11/265 , H03K5/131
摘要： Described are integrated-circuit delay lines that include regulated and unregulated delay elements connected in series. The regulated delay elements exhibit relatively long delays that are stable over process, voltage, and temperature. The unregulated delay elements exhibit relatively short delays with fine adjustment granularity. A multiplexer selects various numbers of the delay elements to provide a range of delay settings. The multiplexer includes a number of smaller multiplexers cascaded to minimize the lead-in delay of the delay element. The delay elements and multiplexer can be single-ended or complementary.
摘要翻译：描述了集成电路延迟线，其包括串联连接的调节和未调节的延迟元件。调节的延迟元件表现出相对较长的延迟，其在工艺，电压和温度上稳定。未调节的延迟元件具有相对较短的延迟和精细的调整粒度。多路复用器选择各种数量的延迟元件来提供一定范围的延迟设置。多路复用器包括多个级联的小型多路复用器，以使延迟元件的导入延迟最小化。延迟元件和多路复用器可以是单端或互补的。

30. 发明申请

WO2011008356A2 TECHNIQUES FOR ADJUSTING CLOCK SIGNALS TO COMPENSATE FOR NOISE 审中-公开
标题翻译：调整时钟信号以补偿噪音的技术
公开(公告)号：WO2011008356A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/036792
申请日：2010-05-31
申请人： RAMBUS INC. , ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
发明人： ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
IPC分类号： H03K19/0175 , H04L25/02 , H03K5/1252
CPC分类号： H04L25/0264 , G06F1/10 , H03K5/1252
摘要： A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
摘要翻译：第一集成电路（IC）具有可调延迟电路和第一接口电路。向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。在其他实施例中，电源电压用于在多个IC上产生时钟信号。

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