专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20130246856A1 VERIFICATION SUPPORTING APPARATUS AND VERIFICATION SUPPORTING METHOD OF RECONFIGURABLE PROCESSOR 有权
标题翻译：验证支持装置和验证支持的可重构处理器的方法
公开(公告)号：US20130246856A1
公开(公告)日：2013-09-19
申请号：US13772647
申请日：2013-02-21
申请人： Young-Chul CHO , Tai-Song JIN , Dong-Kwan SUH , Yen-Jo HAN
发明人： Young-Chul CHO , Tai-Song JIN , Dong-Kwan SUH , Yen-Jo HAN
IPC分类号： G06F11/36
CPC分类号： G06F11/3604 , G06F8/4452 , G06F11/3664 , G06F17/5027
摘要： A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.
摘要翻译：提供了一种可重构处理器的验证支持装置和验证支持方法。验证支持装置包括：无效操作确定器，被配置为根据源代码的调度结果来检测无效操作，以及掩蔽提示生成器，被配置为生成用于检测到的无效操作的屏蔽提示。

22. 发明申请

US20130201765A1 POWER MIXING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：功率混合电路和包括其的半导体存储器件
公开(公告)号：US20130201765A1
公开(公告)日：2013-08-08
申请号：US13619793
申请日：2012-09-14
申请人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
发明人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
IPC分类号： G11C5/14 , G11C7/10 , G06G7/12
CPC分类号： G11C5/147 , G11C5/04 , G11C5/148 , G11C7/02 , G11C7/1012 , G11C7/1057 , G11C7/20
摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.
摘要翻译：提供了能够在深度断电模式下保持稳定的输出电压的功率混合电路。功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。

23. 发明申请

US20120124343A1 APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND 审中-公开
标题翻译：修改指令操作的装置和方法
公开(公告)号：US20120124343A1
公开(公告)日：2012-05-17
申请号：US13163218
申请日：2011-06-17
申请人： Ho-Young Kim , Soo-Jung Ryu , Moo-Kyoung Chung , Woong Seo , Young-Chul Cho
发明人： Ho-Young Kim , Soo-Jung Ryu , Moo-Kyoung Chung , Woong Seo , Young-Chul Cho
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3017 , G06F9/30192 , G06F9/3887
摘要： Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second instruction operand, and to modify the selected first instruction operand and the selected second instruction operand to reduce the operand instructions that are input to the first selector and the second selector.
摘要翻译：提供了一种用于修改指令操作数的装置和方法。该装置包括被配置为接收第一指令操作数的第一选择器和被配置为接收第二指令操作数的第二选择器。该装置还包括：修改单元，被配置为选择第一指令操作数和第二指令操作数，并且修改所选择的第一指令操作数和所选择的第二指令操作数，以减少输入到第一选择器和第二选择器的操作数指令。

24. 发明申请

US20120113128A1 COMPUTING APPARATUS AND METHOD USING X-Y STACK MEMORY 有权
标题翻译：使用X-Y堆叠存储器的计算机和方法
公开(公告)号：US20120113128A1
公开(公告)日：2012-05-10
申请号：US13171772
申请日：2011-06-29
申请人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
发明人： Soo-Jung Ryu , Sung-Bae Park , Woong Seo , Young-Chul Cho , Jeong-Wook Kim , Moo-Kyoung Chung , Ho-Young Kim
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
摘要翻译：提供了一种计算装置。计算装置包括存储单元，其被配置为具有被定义为具有至少两个轴的多维空间的地址空间，以及存储器访问单元，其被配置为包括存储指向与第一轴对应的行的第一指针的第一指针寄存器，以及存储指向对应于第二轴的列的第二指针的第二指针寄存器。

25. 发明申请

US20120089808A1 MULTIPROCESSOR USING A SHARED VIRTUAL MEMORY AND METHOD OF GENERATING A TRANSLATION TABLE 有权
标题翻译：使用共享的虚拟内存的多路由器和生成翻译表的方法
公开(公告)号：US20120089808A1
公开(公告)日：2012-04-12
申请号：US13074999
申请日：2011-03-29
申请人： Choon-Ki Jang , Jaejin Lee , Soo-Jung Ryu , Bernhard Egger , Yoon-Jin Kim , Woong Seo , Young-Chul Cho
发明人： Choon-Ki Jang , Jaejin Lee , Soo-Jung Ryu , Bernhard Egger , Yoon-Jin Kim , Woong Seo , Young-Chul Cho
IPC分类号： G06F12/10
CPC分类号： G06F12/1072 , Y02D10/13
摘要： A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address.
摘要翻译：提供了使用共享虚拟内存（SVM）的多处理器。所述多处理器包括多个处理核心和存储器管理器，所述存储器管理器被配置为将虚拟地址变换为物理地址，以允许处理核心访问对应于所述物理地址的存储器区域。

26. 发明授权

US07304520B2 Delay circuit and semiconductor device including same 有权
标题翻译：延迟电路和包括其的半导体器件
公开(公告)号：US07304520B2
公开(公告)日：2007-12-04
申请号：US11332148
申请日：2006-01-17
申请人： Young-Chul Cho , Joung-Yeal Kim , Sung-Hoon Kim
发明人： Young-Chul Cho , Joung-Yeal Kim , Sung-Hoon Kim
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when a delay operation is enabled based on a corresponding control signal. However, where the delay operation of a delay block is disabled based on the corresponding control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.
摘要翻译：延迟电路包括串联连接的多个延迟块和适于逻辑组合由多个延迟块发送的信号以产生延迟电路输出信号的驱动部分。多个延迟块中的每一个延迟来自紧接在前的延迟块的输出信号，并且当基于相应的控制信号启用延迟操作时，将结果延迟的输出信号发送到下一个延迟块。然而，在延迟块的延迟操作基于相应的控制信号被禁用的情况下，延迟块将紧接在前的延迟块的输出信号发送到驱动部分。

27. 发明申请

US20070171393A1 Laser straight ruler and method for measuring distance and projecting line using the straight ruler 失效
标题翻译：激光直尺和使用直尺测量距离和投影线的方法
公开(公告)号：US20070171393A1
公开(公告)日：2007-07-26
申请号：US11477631
申请日：2006-06-30
申请人： Young-chul Cho , Seok-mo Chang
发明人： Young-chul Cho , Seok-mo Chang
IPC分类号： G01C3/08 , G01B11/14
CPC分类号： G01C3/10 , G01C3/08 , G01C15/004 , G01S17/48
摘要： A laser straight ruler having a main body and a beam scanner installed on the main body. A laser beam is scanned to form a beam spot on an object. A position sensing device receives a laser beam reflected by the object and senses a position of the beam spot. A signal processing unit drives the beam scanner and processes a signal of the position sensing device. A display displays a change in a distance between the main body and the object and data including a measured distance value from the signal processing unit. An input portion inputs data including adjustment of a scanning width of the beam spot and sets start and end positions of the measured distance. A straight distance of the object is measured or the beam spot having a scanning width corresponding to a measured distance or a predetermined distance is projected to the object.
摘要翻译：具有主体和安装在主体上的光束扫描仪的激光直尺。扫描激光束以在物体上形成束斑。位置检测装置接收由物体反射的激光束并感测光斑的位置。信号处理单元驱动光束扫描器并处理位置检测装置的信号。显示器显示主体和对象之间的距离的变化以及包括来自信号处理单元的测量距离值的数据。输入部分输入包括调整光斑的扫描宽度的数据，并设置测量距离的开始和结束位置。测量物体的直线距离，或者将具有对应于测量距离或预定距离的扫描宽度的束斑投射到物体。

28. 发明申请

US20060060986A1 Semiconductor memory device and power line arrangement method thereof 有权
公开(公告)号：US20060060986A1
公开(公告)日：2006-03-23
申请号：US11229257
申请日：2005-09-16
申请人： Sung-Hoon Kim , Young-Chul Cho , Kwang-Il Park , Seong-Jin Jang
发明人： Sung-Hoon Kim , Young-Chul Cho , Kwang-Il Park , Seong-Jin Jang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads.

29. 发明授权

US09130557B2 Operating method of input/output interface 有权
标题翻译：输入/输出接口的操作方法
公开(公告)号：US09130557B2
公开(公告)日：2015-09-08
申请号：US14093916
申请日：2013-12-02
申请人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
发明人： Young Chul Cho , Jung Bae Lee , Jung Hwan Choi
IPC分类号： H03K17/16 , H03K19/003 , H03K19/00
CPC分类号： G06F13/16 , G05F1/625 , G06F1/3287 , G06F13/4068 , G06F13/4221 , H03K19/0005 , Y02D10/14 , Y02D10/151
摘要： A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
摘要翻译：操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

30. 发明授权

US09086959B2 Apparatus to access multi-bank memory 有权
标题翻译：用于访问多行存储器的设备
公开(公告)号：US09086959B2
公开(公告)日：2015-07-21
申请号：US12902681
申请日：2010-10-12
申请人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , Il-Hyun Park , Tae-Wook Oh
发明人： Woong Seo , Soo-Jung Ryu , Yoon-Jin Kim , Young-Chul Cho , Il-Hyun Park , Tae-Wook Oh
IPC分类号： G06F12/10 , G06F12/06 , G06F3/06 , G06F12/02
CPC分类号： G06F12/0607 , G06F3/067 , G06F12/0215 , G06F12/0292
摘要： A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.
摘要翻译：提供一种控制对多存储体存储器的访问的方法以及执行该方法的装置。对于访问控制，提供步幅寄存器以在运行时间期间存储由处理器确定的步幅值。存储器控制器以交错方式控制行和列方向上的逻辑块的访问，该逻辑块具有根据存储在步幅寄存器中的步幅值确定的宽度。因此，可以在行和列方向相邻的连续地址处同时访问多条数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式