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21. 发明授权

US4854936A Semiconductive ceramic composition and semiconductive ceramic capacitor 失效
标题翻译：半导体陶瓷组合物和半导体陶瓷电容器
公开(公告)号：US4854936A
公开(公告)日：1989-08-08
申请号：US272139
申请日：1988-11-15
申请人： Shuichi Ono , Shuichi Itagaki , Masahiro Yahagi , Kiyoshi Furukawa , Shinobu Fujiwara , Yasunobu Oikawa
发明人： Shuichi Ono , Shuichi Itagaki , Masahiro Yahagi , Kiyoshi Furukawa , Shinobu Fujiwara , Yasunobu Oikawa
IPC分类号： C04B35/47 , H01G4/008 , H01G4/12
CPC分类号： H01G4/008 , C04B35/47 , H01G4/1281 , Y10T29/417 , Y10T29/435
摘要： A semiconductive ceramic composition capable of exhibiting excellent electrical and physical characteristics sufficient to be used for a boundary-layer type semiconductive ceramic capacitor and such a capacitor capable of being increased in dielectric constant and insulation resistance and exhibiting excellent solderability and tensile strength of electrodes. The composition includes a SrTiO.sub.3 base material and an additive for semiconductivity consisting of Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5. The Y.sub.2 O.sub.3 and Nb.sub.2 O.sub.5 each are present in an amount of 0.1 to 0.4 mol % based on the composition. The capacitor includes a semiconductive ceramic body formed of the composition, a first conductive layer formed on each of both surfaces of the body and a second conductive layer formed on the first conductive layer. A process for manufacturing the capacitor is also provided.

22. 发明申请

US20110075319A1 THIN-FILM CAPACITOR 有权
标题翻译：薄膜电容器
公开(公告)号：US20110075319A1
公开(公告)日：2011-03-31
申请号：US12876611
申请日：2010-09-07
申请人： Yasunobu OIKAWA , Yoshihiko Yano
发明人： Yasunobu OIKAWA , Yoshihiko Yano
IPC分类号： H01G4/008 , H01G4/005
CPC分类号： H01G4/005 , H01G4/008 , H01G4/33
摘要： To provide a thin-film capacitor capable of preventing the degradation of electrical characteristics caused by direct contact between an adhesion layer of a terminal electrode and a dielectric layer, to increase the reliability. The thin-film capacitor comprises: a dielectric layer deposited on a base electrode; an upper electrode layer deposited on the dielectric layer; a terminal electrode including an adhesion layer, a seed layer, and a plating layer; a resin layer for wiring provided between the upper electrode layer and the terminal electrode for isolating the upper electrode layer from the terminal electrode; and a wiring layer provided so as to extend through the resin layer for wiring in contact with the adhesion layer for electrically connecting the upper electrode layer and the terminal electrode, wherein a composition of the wiring layer differs from that of the adhesion layer of the terminal electrode, and wherein a reducing power of the wiring layer to the dielectric layer is smaller than that of the adhesion layer.
摘要翻译：提供能够防止由端子电极和电介质层的粘附层之间的直接接触引起的电特性劣化的薄膜电容器，以提高可靠性。薄膜电容器包括：沉积在基极上的电介质层; 沉积在电介质层上的上电极层; 包括粘合层，种子层和镀层的端子电极; 用于在上电极层和端子电极之间设置用于将上电极层与端子电极隔离的布线用树脂层; 以及布线层，其设置成延伸穿过用于电连接上电极层和端子电极的粘合层接触的布线用树脂层，其中布线层的组成与端子的粘合层的组成不同电极，并且其中所述布线层到所述电介质层的还原能力小于所述粘合层的还原能力。

23. 发明授权

US07015556B2 Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device 有权
标题翻译：包装基板及其制造方法，集成电路装置及其制造方法以及锯装置
公开(公告)号：US07015556B2
公开(公告)日：2006-03-21
申请号：US10813393
申请日：2004-03-31
申请人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
发明人： Masahiro Nakano , Katsuhiko Gunji , Yasunobu Oikawa , Katsuo Sato
IPC分类号： H01L29/84 , H01L22/48
CPC分类号： H03H9/1071 , H01L2224/16225 , H01L2224/45144 , H03H9/0585 , H03H9/059 , H03H9/08 , H01L2924/00
摘要： A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23 are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 μmRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.
摘要翻译：衬底电极12a的基本部分层21，其在陶瓷的衬底构件上电连接到突出电极13。对其上形成有碱性部分层21的基材进行烧结。研磨烧结基板部件中的基体部分层21的表面。在抛光的基底层21上形成镀层22,23，使得基板电极12a的表面粗糙度例如可以不大于0.1μmumRMS。因此，可以提高通过倒装芯片方法安装在封装基板上的集成电路元件的结合强度。

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