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21. 发明授权

US08058658B2 High-speed optical interconnection device 有权
标题翻译：高速光互连装置
公开(公告)号：US08058658B2
公开(公告)日：2011-11-15
申请号：US12421130
申请日：2009-04-09
申请人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
发明人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
IPC分类号： H01L27/15
CPC分类号： H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
摘要： Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.
摘要翻译：提供了一种高速光互连装置。高速光互连装置包括设置在绝缘体上硅（SOI））衬底上的第一半导体芯片，发光体，光检测器和第二半导体芯片。光发射器接收来自第一半导体芯片的电信号以输出光信号。光检测器检测光信号，将光信号转换为电信号。第二半导体芯片接收由光学检测器转换的电信号。

22. 发明申请

US20100133551A1 HIGH-SPEED OPTICAL INTERCONNECTION DEVICE 有权
标题翻译：高速光学互连器件
公开(公告)号：US20100133551A1
公开(公告)日：2010-06-03
申请号：US12421130
申请日：2009-04-09
申请人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae-Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
发明人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae-Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
IPC分类号： H01L31/147 , H01L33/00
CPC分类号： H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
摘要： Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.
摘要翻译：提供了一种高速光互连装置。高速光互连装置包括设置在绝缘体上硅（SOI））衬底上的第一半导体芯片，发光体，光检测器和第二半导体芯片。光发射器接收来自第一半导体芯片的电信号以输出光信号。光检测器检测光信号，将光信号转换为电信号。第二半导体芯片接收由光学检测器转换的电信号。

23. 发明申请

US20090146184A1 SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有T型电极的半导体器件及其制造方法
公开(公告)号：US20090146184A1
公开(公告)日：2009-06-11
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
发明人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
IPC分类号： H01L29/812 , H01L21/335
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

24. 发明授权

US07429894B2 Power device having connection structure compensating for reactance component of transmission line 失效
标题翻译：具有补偿传输线电抗分量的连接结构的功率器件
公开(公告)号：US07429894B2
公开(公告)日：2008-09-30
申请号：US11519668
申请日：2006-09-12
申请人： Woo Jin Chang , Jae Kyoung Mun , Haecheon Kim , Jong Won Lim , Hong Gu Ji , Ho Kyun Ahn
发明人： Woo Jin Chang , Jae Kyoung Mun , Haecheon Kim , Jong Won Lim , Hong Gu Ji , Ho Kyun Ahn
IPC分类号： H03F3/68
CPC分类号： H03F3/602 , H03F3/211 , H03F2200/366 , H03F2200/447 , H03F2200/543 , H03F2203/21178
摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.
摘要翻译：提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

25. 发明授权

US07106153B2 Waveguide interconnection apparatus 有权
标题翻译：波导互连设备
公开(公告)号：US07106153B2
公开(公告)日：2006-09-12
申请号：US10788435
申请日：2004-03-01
申请人： Woo Jin Chang , Hea Cheon Kim
发明人： Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01P1/02
CPC分类号： H01P1/022 , H01P1/042
摘要： Provided is a waveguide interconnection apparatus making rectangular interconnecting portions to be a curved structure, whereby it is possible to reduce a signal reflection and a signal loss due to a mismatch occurred from a discontinuous portion where waveguides are perpendicularly connected to each other, and fabricate package products having excellent performances compared to that of the prior art in the same chip and structure.
摘要翻译：提供一种使矩形互连部分成为弯曲结构的波导互连装置，由此可以减少信号反射和由波导彼此垂直连接的不连续部分发生的失配引起的信号丢失，并且制造封装产品在相同的芯片和结构中具有优于现有技术的性能。

26. 发明授权

US08772833B2 Power semiconductor device and fabrication method thereof 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08772833B2
公开(公告)日：2014-07-08
申请号：US13592560
申请日：2012-08-23
申请人： Woo Jin Chang , Jong Won Lim , Ho Kyun Ahn , Sang Choon Ko , Sung Bum Bae , Chull Won Ju , Young Rak Park , Jae Kyoung Mun , Eun Soo Nam
发明人： Woo Jin Chang , Jong Won Lim , Ho Kyun Ahn , Sang Choon Ko , Sung Bum Bae , Chull Won Ju , Young Rak Park , Jae Kyoung Mun , Eun Soo Nam
IPC分类号： H01L29/15
CPC分类号： H01L29/66901 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
摘要翻译：公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

27. 发明申请

US20130069127A1 FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20130069127A1
公开(公告)日：2013-03-21
申请号：US13556377
申请日：2012-07-24
申请人： Ho Kyun AHN , Jong-Won Lim , Sung Bum Bae , Sang Choon Ko , Young Rak Park , Woo Jin Chang , Jae Kyoung Mun , Eun Soo Nam , Jeong Jin Kim , Chull Won Ju
发明人： Ho Kyun AHN , Jong-Won Lim , Sung Bum Bae , Sang Choon Ko , Young Rak Park , Woo Jin Chang , Jae Kyoung Mun , Eun Soo Nam , Jeong Jin Kim , Chull Won Ju
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/66863 , H01L29/8128
摘要： A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.
摘要翻译：根据本公开的示例性实施例的制造场效应晶体管的方法包括：在衬底上形成有源层，覆盖层，欧姆金属层和绝缘层; 在所述绝缘层上形成多层光致抗蚀剂; 图案化多层光致抗蚀剂以形成包括用于栅电极的第一开口和场电极的第二开口的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻绝缘层，使得第一开口中的绝缘层被更深地蚀刻并且盖层通过第一开口暴露; 通过蚀刻绝缘层通过第一开口蚀刻暴露的盖层，以形成栅极凹陷区域; 以及在所述栅极凹部区域和所述蚀刻绝缘层上沉积金属以形成栅极电极层。

28. 发明授权

US08192942B2 Affinity separation by partition enhancing material conjugated biomolecules in aqueous two-phase extraction system 有权
标题翻译：通过分层增强材料共轭生物分子在水相两相萃取系统中的亲和力分离
公开(公告)号：US08192942B2
公开(公告)日：2012-06-05
申请号：US12303364
申请日：2008-01-21
申请人： Yoon-Mo Koo , Woo-Jin Chang , Hye-Mee Park
发明人： Yoon-Mo Koo , Woo-Jin Chang , Hye-Mee Park
IPC分类号： G01N33/53 , G01N33/535 , G01N33/536 , C12Q1/28
CPC分类号： C07K1/22
摘要： The present invention relates to a method for separating a material that has affinity to an antibody by using a protein-antibody conjugate with modified partition characteristics, more precisely a method for affinity separation to separate a material specifically binds to an antibody, in which an antibody is conjugated to a protein to modify partition characteristics of the protein-antibody conjugate. The method of the present invention can be effectively and widely used as a safe and efficient separation method for biomolecules since it takes advantages of safe aqueous two-phase extraction system and high selective molecular specific conjugation.
摘要翻译：本发明涉及通过使用具有改良的分隔特征的蛋白质 - 抗体缀合物分离对抗体具有亲和力的材料的方法，更准确地说，分离材料以分离材料特异性结合抗体的方法，其中抗体与蛋白质缀合以改变蛋白质 - 抗体缀合物的分配特征。本发明的方法可以有效和广泛地用作生物分子的安全有效的分离方法，因为它具有安全的水相两相萃取系统和高选择性分子特异性共轭的优点。

29. 发明申请

US20090233756A1 CARRIER CUP OF PLANET CARRIER 有权
标题翻译：运输车载体
公开(公告)号：US20090233756A1
公开(公告)日：2009-09-17
申请号：US12179213
申请日：2008-07-24
申请人： Wang Kweon Lee , Hyun Ku Lee , Sang Bum Baek , Ki Jung Han , Seok Chan Kang , Jae Hyuk Choi , Kisoo Huh , Hyu Tae Shim , Woo Jin Chang
发明人： Wang Kweon Lee , Hyun Ku Lee , Sang Bum Baek , Ki Jung Han , Seok Chan Kang , Jae Hyuk Choi , Kisoo Huh , Hyu Tae Shim , Woo Jin Chang
IPC分类号： F16H57/08
CPC分类号： F16H57/082
摘要： The present invention relates to a carrier cup of a planet carrier that improves strength thereof and reduces noise occurring in an automatic transmission by changing an interior circumferential shape of a leg. The carrier cup of a planet carrier according to an exemplary embodiment of the present invention at which pinion gears are mounted such that the pinion gears are rotatably supported thereby may include a carrier plate provided with a carrier hole for mounting a carrier shaft and a plurality of pinion holes for mounting the pinion gears, and a plurality of legs extending perpendicularly from one side surface of the carrier plate, wherein radial thickness of the leg is changed along a circumferential direction thereof.
摘要翻译：本发明涉及一种行星架的承载杯，其通过改变腿的内部圆周形状来改善其强度并减少在自动变速器中发生的噪音。根据本发明的示例性实施例的行星架的行星架，其中安装小齿轮使得小齿轮由其可旋转地支撑，其可以包括：承载板，其设置有用于安装行星架轴的承载孔和多个用于安装小齿轮的小齿轮孔和从承载板的一个侧表面垂直延伸的多个腿，其中腿的径向厚度沿其圆周方向改变。

30. 发明申请

US20090170250A1 TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20090170250A1
公开(公告)日：2009-07-02
申请号：US12396614
申请日：2009-03-03
申请人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
发明人： Jae Kyoung MUN , Jong Won LIM , Woo Jin CHANG , Hong Gu JI , Ho Kyun AHN , Hae Cheon KIM
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L29/7785
摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.
摘要翻译：提供半导体器件的晶体管及其制造方法。晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层，所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。在这种结构中，可以提高晶体管的隔离和开关速度。此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

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