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21. 发明授权

US06440779B1 Semiconductor package based on window pad type of leadframe and method of fabricating the same 失效
标题翻译：基于窗框焊接引线框的半导体封装及其制造方法
公开(公告)号：US06440779B1
公开(公告)日：2002-08-27
申请号：US09859098
申请日：2001-05-16
申请人： Fly Chiu , Audi Chen , Tzong-Da Ho
发明人： Fly Chiu , Audi Chen , Tzong-Da Ho
IPC分类号： H01L2148
CPC分类号： H01L23/49568 , H01L23/16 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/01079 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A new semiconductor packaging technology is proposed for the fabrication of a semiconductor package based on window pad type of leadframe. The proposed semiconductor packaging technology is characterized by the mounting of a window shim having a solid ring portion and a hollowed window portion over the die pad of the leadframe. The window shim is dimensioned in such a manner that the width of the ring portion thereof is larger than the width of the window portion of the die pad of the leadframe, while the width of the window portion of the window shim is smaller than the width of the semiconductor chip. This feature allows one design of the window pad type of leadframe to be universally suited for packaging semiconductor chips of various sizes. Moreover, the incorporation of the window shim additionally allows an increase in the heat-dissipation efficiency of the packaged chip.
摘要翻译：提出了一种新的半导体封装技术，用于制造基于窗框式引线框的半导体封装。所提出的半导体封装技术的特征在于在引线框的芯片焊盘的上方安装具有实心环部分和中空的窗口部分的窗垫片。窗扇的尺寸设计成使得其环部的宽度大于引线框架的管芯焊盘的窗口部分的宽度，而窗垫片的窗口部分的宽度小于宽度的半导体芯片。该特征允许引线框的窗口垫类型的一种设计通常适合于封装各种尺寸的半导体芯片。此外，还增加了窗口垫片的结合，可以提高封装芯片的散热效率。

22. 发明授权

US06359341B1 Ball grid array integrated circuit package structure 失效
标题翻译：球栅阵列集成电路封装结构
公开(公告)号：US06359341B1
公开(公告)日：2002-03-19
申请号：US09489167
申请日：2000-01-21
申请人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
发明人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
IPC分类号： H01L2940
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49816 , H01L23/50 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H05K3/341 , H05K3/3436 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A BGA (Ball Grid Array) integrated circuit package is proposed, which is characterized in the use of a ground metallic layer adhered to a substrate. Moreover, the ground metallic layer can provide the semiconductor chip with a heat-dissipation path, allowing heat from the semiconductor chip during operation to be dissipated to the atmosphere via the ground metallic layer, so that the overall heat-dissipation efficiency can be increased. The ground metallic layer is formed with a chip-receiving cavity for accommodating a semiconductor chip mounted on the substrate. As the semiconductor chip is surrounded and in close proximity to the ground metallic layer, it can help reduce undesired simultaneous switching noise, crosstalk, and electromagnetic interference in the integrated circuit package.
摘要翻译：提出了一种BGA（球栅阵列）集成电路封装，其特征在于使用附着在基板上的接地金属层。此外，接地金属层可以为半导体芯片提供散热路径，允许来自半导体芯片的工作中的热量经由接地金属层散发到大气中，从而可以提高总的散热效率。接地金属层形成有用于容纳安装在基板上的半导体芯片的芯片接收腔。当半导体芯片被围绕并且紧邻接地金属层时，它可以帮助减少集成电路封装中的不期望的同时开关噪声，串扰和电磁干扰。

23. 发明授权

US06306682B1 Method of fabricating a ball grid array integrated circuit package having an encapsulating body 有权
标题翻译：制造具有封装体的球栅阵列集成电路封装的方法
公开(公告)号：US06306682B1
公开(公告)日：2001-10-23
申请号：US09547157
申请日：2000-04-11
申请人： Chien-Ping Huang , Randy H. Y. Lo , Tzong-Da Ho , Eric Ko , Jui-Meng Jao
发明人： Chien-Ping Huang , Randy H. Y. Lo , Tzong-Da Ho , Eric Ko , Jui-Meng Jao
IPC分类号： H01L2144
CPC分类号： H01L21/56 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/92247 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A method of fabricating a BGA (Ball Grid Array) IC package of the type having an encapsulating body is proposed, which allows the BGA IC package to be manufactured without having to use conventional organic substrate and encapsulating-body mold having cavity, so that the manufacture process can be more cost-effective to carry out than the prior art. The proposed method is characterized in the use of a copper piece which is selectively removed to form an encapsulating-body cavity for the forming of an encapsulating body therein. The proposed method requires no use of mold with cavity for the forming of the encapsulating body, allowing the same mold to be used for the fabrication of various BGA IC packages of different sizes. Moreover, the proposed method allows fan-in design as well as fan-out design, thus allowing the number of I/O ports to be increased while making the overall package configuration compact in size, and also allows the implantation of the electrically-conductive balls to be easier to carry out and more precisely controlled than the prior art, making the ball implantation more assured in quality than the prior art. Therefore, the proposed method is more advantageous and cost-effective to use than the prior art.
摘要翻译：提出了一种制造具有封装体的BGA（球栅阵列）IC封装的方法，其允许制造BGA IC封装，而不必使用传统的有机衬底和具有空腔的封装体模具，制造工艺比现有技术更具成本效益。所提出的方法的特征在于使用铜片，其被选择性地去除以形成用于在其中形成封装体的封装体腔体。所提出的方法不需要使用具有空腔的模具来形成封装体，允许相同的模具用于制造不同尺寸的各种BGA IC封装。此外，所提出的方法允许风扇设计以及扇出式设计，从而允许增加I / O端口的数量，同时使整个封装结构的尺寸紧凑，并且还允许将导电球比现有技术更容易实施和更精确地控制，使得球注入在质量上比现有技术更加确保。因此，所提出的方法比现有技术更有利且成本有效。

24. 再颁专利

USRE39957E1 Method of making semiconductor package with heat spreader 有权
标题翻译：用散热器制造半导体封装的方法
公开(公告)号：USRE39957E1
公开(公告)日：2007-12-25
申请号：US10934632
申请日：2004-09-03
申请人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
IPC分类号： H01C21/66 , H01C21/00 , H01L21/44 , H01L23/28 , H01L25/29 , H01L23/48 , H01L23/34 , H01L23/10
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599 , H01L2224/0401
摘要： A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.
摘要翻译：提供了一种制造具有散热器的半导体封装的方法，其中由多个阵列布置的芯片载体组成的芯片载体模块板在每个芯片载体上安装有至少一个芯片。散热器模块板附接到芯片，其中界面层形成在散热器模块板的顶表面上。芯片载体模块板，芯片和散热器模块板被封装。界面层与密封剂之间的粘附力大于界面层与散热器模块板之间的粘合力，界面层与散热器模块板之间的粘合力小于散热器模块板与密封剂之间的粘附力。

25. 发明授权

US06707167B2 Semiconductor package with crack-preventing member 有权
标题翻译：具防裂构件的半导体封装
公开(公告)号：US06707167B2
公开(公告)日：2004-03-16
申请号：US10026594
申请日：2001-12-20
申请人： Chien-Ping Huang , Tzong-Da Ho
发明人： Chien-Ping Huang , Tzong-Da Ho
IPC分类号： H01L2348
CPC分类号： H01L23/562 , H01L23/24 , H01L23/3107 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package with a crack-preventing member is proposed, in which a chip is mounted on a chip carrier by means of an adhesive and is electrically connected to the chip carrier. The crack-preventing member is formed at a proper position on the chip, and generates compression stress on the chip to sufficiently counteract tension stress produced from the chip carrier and adhesive in a molding process. This can effectively prevent the chip from cracking during molding, and thus improve the quality of fabricated products.
摘要翻译：提出了具有防裂构件的半导体封装，其中通过粘合剂将芯片安装在芯片载体上并与芯片载体电连接。防裂构件形成在芯片上的适当位置，并且在模制过程中在芯片上产生压缩应力以充分抵消由芯片载体和粘合剂产生的张力。这可以有效地防止芯片在成型过程中发生裂纹，从而提高制造产品的质量。

26. 发明授权

US06541870B1 Semiconductor package with stacked chips 有权
标题翻译：半导体封装堆叠芯片
公开(公告)号：US06541870B1
公开(公告)日：2003-04-01
申请号：US09990788
申请日：2001-11-14
申请人： Chien-Ping Huang , Tzong-Da Ho , cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Tzong-Da Ho , cheng-Hsu Hsiao
IPC分类号： H01L2348
CPC分类号： H01L25/0657 , H01L23/3121 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/01079 , H01L2924/10161 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor package with stacked chips is proposed, wherein at least two chips are stacked on a chip carrier in a stagger manner as to dispose a second chip on a first chip, and a supporting element is disposed on the second chip and dimensioned to cover area on the second chip with no support from the first chip. The supporting element provides support to the second chip, allowing bonding wires to be successfully connected to the second chip, without the occurrence of cracks of the second chip. The supporting element can be formed on its lower surface with protruding portions positioned outside edge sides of the second chip; this is to enhance structural strength of the supporting element, and help maintain the second chip intact in structure during wire bonding. The supporting element can further have its upper surface to be exposed to the atmosphere; this improves heat dissipating efficiency of the semiconductor package.
摘要翻译：提出了一种具有堆叠芯片的半导体封装，其中至少两个芯片以错开的方式堆叠在芯片载体上，以将第二芯片布置在第一芯片上，并且支撑元件设置在第二芯片上并且尺寸设置为覆盖区域在第二个芯片上没有第一个芯片的支持。支撑元件为第二芯片提供支撑，允许接合线成功地连接到第二芯片，而不会发生第二芯片的裂纹。支撑元件可以在其下表面上形成有位于第二芯片的边缘侧的突出部分; 这是为了增强支撑元件的结构强度，并且有助于在引线接合期间保持第二芯片的结构完整。支撑元件还可以使其上表面暴露于大气中; 这提高了半导体封装的散热效率。

27. 发明授权

US06469897B2 Cavity-down tape ball grid array package assembly with grounded heat sink and method of fabricating the same 失效
公开(公告)号：US06469897B2
公开(公告)日：2002-10-22
申请号：US09774211
申请日：2001-01-30
申请人： Tzong-Da Ho , Chien-Ping Huang , Han-Ping Pu
发明人： Tzong-Da Ho , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H05K720
CPC分类号： H01L23/49816 , H01L23/36 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01047 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , Y10T29/4935 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A TBGA (Tape Ball Grid Array) package assembly with grounded heat sink and method of fabricating the same is provided, which is constructed of a tape, a heat sink, and at least one semiconductor chip. The proposed TBGA technology is characterized by that a grounding plug is formed by first forming a via hole in the heat sink and a via hole in the tape without penetrating through the grounding solder-ball pad, and then filling an electrically-conductive material, such as solder or silver paste, into the heat-sink via hole from the top of the package assembly until filling up the tape via hole and the heat-sink via hole. As the semiconductor chip is mounted in position, its grounding pads are electrically bonded to the heat sink, thereby allowing the semiconductor chip to be externally grounded through the grounding plug, the grounding solder-ball pad, and the solder ball attached to the grounding solder-ball pad. The proposed TBGA technology allows the resulted grounding plug to be firmly secured in position due to the filled solder being wettable to the heat sink, thereby providing a greater ball shear strength to the grounding solder ball that is subsequently bonded to the grounding plug. The finished TBGA package would be therefore assured in the reliability of its grounding structure.

28. 发明授权

US06449169B1 Ball grid array package with interdigitated power ring and ground ring 有权
标题翻译：球形阵列封装，带有交错电源环和接地环
公开(公告)号：US06449169B1
公开(公告)日：2002-09-10
申请号：US09796316
申请日：2001-02-28
申请人： Tzong-Da Ho , Chih-Chin Liao , Chien-Te Chen
发明人： Tzong-Da Ho , Chih-Chin Liao , Chien-Te Chen
IPC分类号： H05K118
CPC分类号： H01L24/49 , H01L23/49827 , H01L23/49838 , H01L24/48 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48235 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/014 , H01L2924/15311 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging. Further, the toothed portions of the power ring and the ground ring are large in area, whereby two or more power vias or ground vias can be gathered together to increase the overall electrical performance, and whereby the packaged chip can be increased in heat-dissipation efficiency.
摘要翻译：提出了一种BGA（球栅阵列）封装，其特征在于提供交叉电源/接地环布局方案。通过该布置方案，功率环和接地环各自形成有线部分和多个齿形部分; 电源环的齿形部分与接地环的齿形部分交错。此外，电源/接地通孔都连接到电源环和接地环的齿形部分，从而使电源环和接地环的线路部分不被电源/接地通孔占据，从而允许电力/ 接地线高于现有技术。此外，焊盘以覆盖接地环的所有齿部的方式形成，从而可以防止电源线由于下垂而与接地环短路。此外，电源环和接地环的齿形部分面积大，由此可以将两个或更多个电源通孔或接地通孔聚集在一起以增加整体电气性能，从而可以增加封装芯片的散热能力效率。

29. 发明授权

US06319750B1 Layout method for thin and fine ball grid array package substrate with plating bus 失效
标题翻译：精细球栅阵列封装基板与电镀母线布局方法
公开(公告)号：US06319750B1
公开(公告)日：2001-11-20
申请号：US09711988
申请日：2000-11-14
申请人： Chien-Ping Huang , Tzong-Da Ho
发明人： Chien-Ping Huang , Tzong-Da Ho
IPC分类号： H01L2144
CPC分类号： H05K3/242 , H01L23/49838 , H01L2924/0002 , H05K3/0052 , H01L2924/00
摘要： A layout method is proposed for semiconductor package substrate with plating bus, such as TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. The proposed layout method is characterized in the provision of a plating bus of a special layout pattern for interconnecting all the via lands alongside each singulation line. The plating bus includes a plurality of crosswise segments, each being used to to interconnect one crosswise-opposite pair of the via lands across the singulation line; and a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line. The proposed layout method allows each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. Moreover, it also allows the layout design work to be less complex than prior art.
摘要翻译：提出了一种具有电镀母线（例如TFBGA（Thin＆Fine Ball Grid Array）薄膜）的半导体封装衬底的布局方法，其可以帮助允许来自衬底的每个单个封装单元由于不对准切割而基本上无痕迹短路在分割过程中。所提出的布局方法的特征在于提供一种专用布局图案的电镀母线，用于将所有通孔焊盘与每条分离线连接。电镀母线包括多个横向段，每个横向段用于将一个横向相对的一对通孔焊盘互相穿过该分离线; 以及多个对角线段，每个对角线段用于将一对相邻的横向线段彼此对角地互相穿过单线。所提出的布局方法允许来自基板的每个单个封装单元在切割过程中由于不对齐切割而基本上没有痕迹短路。此外，它还允许布局设计工作比现有技术更不复杂。

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