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    • 22. 发明授权
    • Memory device having row decoder
    • 具有行解码器的存储器件
    • US6111795A
    • 2000-08-29
    • US342059
    • 1999-06-29
    • Masato TakitaMasato MatsumiyaMasatomo HasegawaToshimi Ikeda
    • Masato TakitaMasato MatsumiyaMasatomo HasegawaToshimi Ikeda
    • G11C11/407G11C8/08G11C8/10G11C8/18G11C11/4076G11C11/408G11C7/00
    • G11C8/08G11C11/4076G11C11/4087G11C8/10G11C8/18
    • On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
    • 一方面,通过缓冲器将行地址提供给行地址寄存器11,并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。 另一方面,响应于激活命令的发出,控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2,并且提供AS2以减少定时 通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。 每个锁存电路由具有设定输入和复位输入的NOR门组成,另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入,以接收对于所有者共同的多选择信号 字解码器中的锁存电路。
    • 24. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US06317353B1
    • 2001-11-13
    • US09536449
    • 2000-03-28
    • Toshimi IkedaMasato MatsumiyaMasato Takita
    • Toshimi IkedaMasato MatsumiyaMasato Takita
    • G11C506
    • G11C5/063G11C5/14
    • A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.
    • 电源线形成在存储单元阵列上,该存储单元阵列使用布置在最靠近存储单元阵列的一侧的金属布线层M1布置了多个存储单元。 电源线不仅使用上金属布线层M2而且金属布线层M1形成在存储单元阵列的上方,使得电源线的布线电阻可能降低,并且能够向电源提供足够的电流量 供应线。 因此,通过电源线提供电流的电路变得能够高速运行。 这对于布置在存储单元阵列周围的电路的高速操作特别有效。 使用下金属布线层M1形成的电源线通过存储单元阵列连接到使用上层的金属布线层M2形成的电源线,而不是金属布线层M1。 因此,与常规电源线相比,可以以更高的密度制造电源线的网状结构。
    • 25. 发明授权
    • Process for producing a semiconductor device
    • 半导体装置的制造方法
    • US5688712A
    • 1997-11-18
    • US643938
    • 1996-05-07
    • Taiji EmaToshimi Ikeda
    • Taiji EmaToshimi Ikeda
    • H01L21/8244H01L27/10H01L27/105H01L27/108H01L27/11H01L21/70
    • H01L27/105H01L27/10817H01L27/11H01L27/1116H01L28/86
    • A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covering the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.
    • 半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域,其间插入有边界区域。 第一导电层覆盖存储单元区域并延伸到边界区域上。 第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。 覆盖第一绝缘层和第一导电层的第二绝缘层。 通过第一绝缘层和第二绝缘层形成通孔。 第二导电层经由通孔与另一导电层电连接,并从存储单元区域延伸到周围电路区域。 还公开了制造半导体器件的工艺。
    • 26. 发明授权
    • Process of producing a semiconductor device in which a height difference
between a memory cell area and a peripheral area is eliminated
    • 制造其中消除了存储单元区域和外围区域之间的高度差的半导体器件的工艺
    • US5591659A
    • 1997-01-07
    • US318261
    • 1994-10-05
    • Taiji EmaToshimi Ikeda
    • Taiji EmaToshimi Ikeda
    • H01L21/8242H01L21/8244H01L27/105H01L21/70H01L27/00
    • H01L27/10844H01L27/105H01L27/11H01L27/1116H01L28/86
    • A semiconductor device comprising: a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area containing a peripheral circuit for controlling the memory cell; an insulating layer covering the peripheral circuit area and being absent in the memory cell area; protective layers effective in etching of the insulating layer and covering the top surfaces and side surfaces of word line conductor patters and bit line conductor patterns in the memory cell area; a contact hole having a circumference defined by one of the protective layers that covers side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and a storage electrode of the capacitor element being connected to the diffused region through the contact hole. A process of producing the semiconductor device is also disclosed.
    • 一种半导体器件,包括:具有包含由电容器元件构成的存储单元的存储单元区域的半导体衬底和包含用于控制存储单元的外围电路的外围电路区域; 覆盖外围电路区域并且不存在于存储单元区域中的绝缘层; 保护层有效地蚀刻绝缘层并覆盖存储单元区域中的字线导体图案和位线导体图案的顶表面和侧表面; 接触孔,其具有由覆盖所述存储单元区域中的字线导体图案的侧表面的保护层之一限定的圆周,所述接触孔延伸到所述半导体衬底中的扩散区域; 并且电容器元件的存储电极通过接触孔连接到扩散区域。 还公开了制造半导体器件的工艺。