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1. 发明授权

US06198686B1 Memory device having row decoder 有权
标题翻译：具有行解码器的存储器件
公开(公告)号：US06198686B1
公开(公告)日：2001-03-06
申请号：US09613583
申请日：2000-07-10
申请人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
发明人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
摘要翻译：一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号字解码器中的锁存电路。

2. 发明授权

US6111795A Memory device having row decoder 有权
标题翻译：具有行解码器的存储器件
公开(公告)号：US6111795A
公开(公告)日：2000-08-29
申请号：US342059
申请日：1999-06-29
申请人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
发明人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/4076 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/4087 , G11C8/10 , G11C8/18
摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
摘要翻译：一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号字解码器中的锁存电路。

3. 发明申请

US20060098523A1 Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
标题翻译：能够将未选择的字线驱动到第一和第二电位的半导体存储器件
公开(公告)号：US20060098523A1
公开(公告)日：2006-05-11
申请号：US11313963
申请日：2005-12-22
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

4. 发明授权

US6147919A Semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access 有权
标题翻译：采用直接式读出放大器的半导体存储器，能够实现高速存取
公开(公告)号：US6147919A
公开(公告)日：2000-11-14
申请号：US274245
申请日：1999-03-23
申请人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
发明人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
IPC分类号： H01L27/10 , G11C7/06 , G11C7/12 , G11C7/02
CPC分类号： G11C7/06 , G11C7/12
摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.
摘要翻译：半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。读出放大器在每行中分组成读出放大器模块。只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器。本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。只写列选择线由用于控制读出放大器的信号控制。

5. 发明申请

US20100220540A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS 审中-公开
公开(公告)号：US20100220540A1
公开(公告)日：2010-09-02
申请号：US12718808
申请日：2010-03-05
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

6. 发明授权

US07706209B2 Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation 失效
标题翻译：能够基于银行存取操作将未选字线驱动到可变负电位的半导体存储器件
公开(公告)号：US07706209B2
公开(公告)日：2010-04-27
申请号：US11313963
申请日：2005-12-22
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/08
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.
摘要翻译：一种半导体器件，包括用于驱动连接到存储单元阵列中的存储单元的字线的字线驱动器，以及当存储器单元从激活状态变为待机状态时重新设定字线。当执行字线的复位时，字线驱动器的复位电平被设置，并且可以在第一和第二电位之间切换。字线复位电平发生电路根据存储单元阵列工作条件改变负电位电流供给量。半导体器件包括多个电源电路，每个电源电路具有振荡电路和电容器，用于经由振荡电路输出的振荡信号来驱动电容器。至少一些电源电路共用一个共同的振荡电路，而不同的电容通过公共振荡信号驱动。

7. 发明授权

US06252269B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06252269B1
公开(公告)日：2001-06-26
申请号：US09422860
申请日：1999-10-25
申请人： Masatomo Hasegawa , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii
发明人： Masatomo Hasegawa , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii
IPC分类号： H01L27108
CPC分类号： H01L21/8249 , H01L27/0214 , H01L27/0623 , H01L27/105 , H01L27/10897
摘要： According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.
摘要翻译：根据本发明的一个方面的半导体存储器，在形成在P型半导体衬底的表面的P型第一阱区域中形成存储单元晶体管，并且将反向偏置电压施加到 P型第一阱区和P型衬底。此外，通过注入高能N型杂质形成N型逆行区域，从而通过采用N型逆行区域形成较深的N型第二阱区域。此外，在N型第二阱区中形成P型第三阱区，并且还在其中形成P型发射极区。因此，P型发射极区域，N型第二阱区域和P型第三阱区域一起构成横向PNP晶体管。此外，为作为集电极区域的P型第三阱区域保持接地电压。

8. 发明授权

US06229363B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06229363B1
公开(公告)日：2001-05-08
申请号：US09224354
申请日：1999-01-04
申请人： Satoshi Eto , Masato Matsumiya , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Satoshi Eto , Masato Matsumiya , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03L708
CPC分类号： G11C7/1057 , G06F1/10 , G11C7/1051 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A semiconductor device having the function of generating an internal clock signal delayed by a predetermined phase by adjusting the phase of an external clock signal, includes a first clock phase circuit for roughly adjusting the phase of the external clock signal; and a second clock phase adjusting circuit for controlling the phase of the internal clock signal with higher accuracy than the first clock phase adjusting circuit. The semiconductor device having such a construction executes phase comparisons by the first and second clock phase adjusting circuits independently of each other, and when a phase control operation by the second clock phase adjusting circuit is made subordinate to that of the first clock phase adjusting circuit, the delay time of each of a plurality of delay elements inside the first clock phase adjusting circuit is set to a value larger than a power source jitter resulting from a noise of a power source and a jitter of the external clock signal.
摘要翻译：具有通过调整外部时钟信号的相位而产生延迟预定相位的内部时钟信号的功能的半导体器件包括用于大致调整外部时钟信号的相位的第一时钟相位电路; 以及第二时钟相位调整电路，用于以比第一时钟相位调整电路更高的精度来控制内部时钟信号的相位。具有这种结构的半导体器件执行第一和第二时钟相位调整电路彼此独立的相位比较，并且当第二时钟相位调整电路的相位控制操作从属于第一时钟相位调整电路的相位控制操作时，第一时钟相位调整电路内的多个延迟元件中的每一个的延迟时间被设定为大于由电源的噪声和外部时钟信号的抖动导致的电源抖动的值。

9. 发明授权

US6115284A Memory device with faster write operation 有权
标题翻译：具有更快写入操作的存储器件
公开(公告)号：US6115284A
公开(公告)日：2000-09-05
申请号：US317902
申请日：1999-05-25
申请人： Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： G11C11/409 , G11C7/00 , G11C7/12 , G11C11/407 , G11C11/4094 , G11C11/24
CPC分类号： G11C11/4094 , G11C7/12
摘要： The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.ds of the cell transistor from being zero by setting the writing voltage (fourth voltage) for H level of the cell capacitor to be lower than the voltage for H level (second voltage) of the bit line, thus reducing a time of writing or re-writing data. Additionally, a pre-charge voltage (first voltage) of the bit lines is set to be lower than the half of the amplitude of the bit line. Thereby, it also becomes possible to prevent the very small voltage of the bit line from being smaller according to the lowered H level voltage in the memory cell.
摘要翻译：本发明涉及包括由连接到位和字线的单元晶体管形成的存储单元和单元电容器的存储器件。存储装置包括用于将位线预充电到第一电压的预充电电路，用于检测位线的电压并将位线驱动为用于H电平的第二电压或L电平的第三电压的读出放大器，以及用于驱动字线以使单元电容器的H电平的写入电压低于低于第二电压的第四电压的字线驱动电路。本发明的特征在于，第一电压低于第二和第三电压之间的中间值。根据本发明，通过将单元电容器的H电平的写入电压（第四电压）设定为低于H电平（第二电压）的电压，可以防止单元晶体管的电压Vds为零，的位线，从而减少写入或重写数据的时间。此外，位线的预充电电压（第一电压）被设置为低于位线的幅度的一半。因此，根据存储单元中的低电平电平，也可以防止位线的非常小的电压变小。

10. 发明申请

US20100321983A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS 审中-公开
标题翻译：能够驱动非选定字线的第一和第二电位的半导体存储器件
公开(公告)号：US20100321983A1
公开(公告)日：2010-12-23
申请号：US12718819
申请日：2010-03-05
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C11/24 , G11C5/14
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

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