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21. 发明授权

US06631174B1 Automatic frequency control apparatus 失效
标题翻译：自动变频调速装置
公开(公告)号：US06631174B1
公开(公告)日：2003-10-07
申请号：US09374261
申请日：1999-08-16
申请人： Takashi Asahara , Toshiharu Kojima
发明人： Takashi Asahara , Toshiharu Kojima
IPC分类号： H04L2706
CPC分类号： H04L27/3818 , H03J7/02 , H04L27/2273 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： A transmitting side periodically inserts a known signal consisting of successive NP symbols into an information signal consisting of (NF−NP) symbols and transmits the NF symbol signal. The receiving side receives the NF symbol signal, and automatically controls a frequency by estimating a frequency deviation from the incoming signal. More specifically, the receiving side outputs I and Q-channel analog baseband signals from the received incoming signal as well as from a sinusoidal signal outputted from an oscillator, and converts the analog baseband signals to the digital baseband signals. Then a phase difference for one symbol cycle is estimated from the digital baseband signals, integration processing is executed by iterative addition of the estimated values, and the frequency deviation is eliminated from the digital baseband signals using a result of the processing for integration.
摘要翻译：发送侧周期性地将由连续的NP符号组成的已知信号插入到由（NF-NP）个符号组成的信息信号中，并发送NF符号信号。接收侧接收NF符号信号，并且通过估计与输入信号的频率偏差来自动控制频率。更具体地，接收侧从接收到的输入信号以及从振荡器输出的正弦信号输出I和Q通道模拟基带信号，并将模拟基带信号转换为数字基带信号。然后，从数字基带信号估计一个符号周期的相位差，通过迭代估计值来执行积分处理，并且使用积分处理的结果从数字基带信号中消除频率偏差。

22. 发明授权

US5844907A Synchronization determining circuit, demodulator and communication system 失效
标题翻译：同步确定电路，解调器和通信系统
公开(公告)号：US5844907A
公开(公告)日：1998-12-01
申请号：US685746
申请日：1996-07-24
申请人： Tatsuya Uchiki , Toshiharu Kojima
发明人： Tatsuya Uchiki , Toshiharu Kojima
IPC分类号： H04L27/22 , H04J3/06 , H04L1/02 , H04L1/08 , H04L7/00 , H04L7/08
CPC分类号： H04J3/06
摘要： A synchronization determining method and circuit for determining a synchronization state of a multiplexed data stream derived by multiplexing a plurality of data streams having the same contents with a time lag provided therebetween, wherein the synchronization determining circuit establishes synchronization without decreasing transmission efficiency, generating incorrect code sequences, or increasing overall circuit scale. In each embodiment of the present invention, synchronization is established without using synchronization words. Because synchronization is achieved without feedback loop delay, incorrectly decoded sequences are not generated for a period of time before synchronization is established. Also, because no maximum pass metric state detecting circuit is required, circuit scale, power consumption, and operating speed can be improved.
摘要翻译：一种同步确定方法和电路，用于确定通过多路复用具有相同内容的多个数据流而产生的多路复用数据流的同步状态，其中同步确定电路在不降低传输效率的情况下建立同步而产生不正确的代码序列，或增加总体电路规模。在本发明的每个实施例中，在不使用同步字的情况下建立同步。由于在没有反馈环路延迟的情况下实现同步，因此在建立同步之前的一段时间内不会产生错误解码的序列。此外，由于不需要最大通过度量状态检测电路，因此可以提高电路规模，功耗和运行速度。

23. 发明授权

US5578947A Delayed detection type demodulator 失效
标题翻译：延迟检测型解调器
公开(公告)号：US5578947A
公开(公告)日：1996-11-26
申请号：US468835
申请日：1995-06-06
申请人： Toshiharu Kojima
发明人： Toshiharu Kojima
IPC分类号： H04L27/38 , H03D7/00 , H03D7/16 , H03D13/00 , H04L27/22 , H04L27/227 , H04L27/233
CPC分类号： H03D7/00 , H03D13/001 , H03D13/003 , H04L27/2332 , H04L27/2337 , H03D2200/007 , H03D7/161 , H03D7/165
摘要： Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means. Alternatively, the phase detection circuit 400 for generating the relative phase signal may include: a half-period detection means 901 consisting of a delay element 401 and an exclusive OR element 402; a phase reference signal generation means 902 consisting of a modulo 2N counter 403; and a phase shift measurement means 903 consisting of a phase inversion corrector 500 and a D flip-flop array 404. The delay element 40 delays the relative phase signal by one symbol period and the subtractor 41 outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit 42 obtains the demodulated data from the phase difference signal.
摘要翻译：在差分检测解调器中，接收信号首先由限幅放大器10量化，然后由包括：异或元件51的变频器50进行频率转换; 由移位寄存器53和加法器54组成的运行平均发生器52; 和比较器55.响应于频率转换器50的输出，相位比较器60相对于相位参考信号输出表示频率转换之后的接收信号的相移的相对相位信号。相位比较器60包括：异或元件61; 由加法器63和D触发器阵列64和65组成的绝对相移测量装置62; 以及用作相移极性判定装置的D触发器66。或者，用于产生相对相位信号的相位检测电路400可以包括：由延迟元件401和异或元件402组成的半周期检测装置901; 由模2N计数器403组成的相位参考信号产生装置902; 以及由相位反相校正器500和D触发器阵列404组成的相移测量装置903.延迟元件40将相对相位信号延迟一个符号周期，并且减法器41输出表示相位转变的相位差信号接收信号的每个符号周期。判定电路42从相位差信号中取得解调数据。

24. 发明授权

US5557222A Delayed detection type demodulator 失效
公开(公告)号：US5557222A
公开(公告)日：1996-09-17
申请号：US218621
申请日：1994-03-28
申请人： Toshiharu Kojima
发明人： Toshiharu Kojima
IPC分类号： H04L27/38 , H03D7/00 , H03D7/16 , H03D13/00 , H04L27/22 , H04L27/227 , H04L27/233
CPC分类号： H03D7/00 , H03D13/001 , H03D13/003 , H04L27/2332 , H04L27/2337 , H03D2200/007 , H03D7/161 , H03D7/165
摘要： Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means. Alternatively, the phase detection circuit 400 for generating the relative phase signal may include: a half-period detection means 901 consisting of a delay element 401 and an exclusive OR element 402; a phase reference signal generation means 902 consisting of a modulo 2N counter 403; and a phase shift measurement means 903 consisting of a phase inversion corrector 500 and a D flip-flop array 404. The delay element 40 delays the relative phase signal by one symbol period and the subtractor 41 outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit 42 obtains the demodulated data from the phase difference signal.

25. 发明授权

US5530382A Delayed detection type demodulator 失效
公开(公告)号：US5530382A
公开(公告)日：1996-06-25
申请号：US219024
申请日：1994-03-28
申请人： Toshiharu Kojima
发明人： Toshiharu Kojima
IPC分类号： H04L27/38 , H03D7/00 , H03D7/16 , H03D13/00 , H04L27/22 , H04L27/227 , H04L27/233
CPC分类号： H03D7/00 , H03D13/001 , H03D13/003 , H04L27/2332 , H04L27/2337 , H03D2200/007 , H03D7/161 , H03D7/165
摘要： Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means. Alternatively, the phase detection circuit 400 for generating the relative phase signal may include: a half-period detection means 901 consisting of a delay element 401 and an exclusive OR element 402; a phase reference signal generation means 902 consisting of a modulo 2N counter 403; and a phase shift measurement means 903 consisting of a phase inversion corrector 500 and a D flip-flop array 404. The delay element 40 delays the relative phase signal by one symbol period and the subtractor 41 outputs the phase difference signal representing the phase transition over each symbol period of the received signal. The decision circuit 42 obtains the demodulated data from the phase difference signal.

26. 发明授权

US5280538A Spread spectrum demodulator 失效
标题翻译：扩频解调器
公开(公告)号：US5280538A
公开(公告)日：1994-01-18
申请号：US838503
申请日：1992-02-18
申请人： Nobuhisa Kataoka , Toshiharu Kojima
发明人： Nobuhisa Kataoka , Toshiharu Kojima
IPC分类号： H04B1/7085 , H04L27/30
CPC分类号： H04B1/7085
摘要： A spread spectrum demodulator for use with a phase-shift-keying modulated spread spectrum signal used in mobile satellite communications. An objective of the spread spectrum demodulator is to perform tracking by producing from a correlation pulse signal an error signal having a time discrimination characteristic. The spread spectrum demodulator generates from the correlation pulse signal an error signal whose level varies in response to a phase difference between a pseudonoise signal contained in a received signal and a reference pseudonoise signal. A clock in synchronism with the received signal is generated from this error signal, thereby demodulating the received signal.
摘要翻译：一种用于移动卫星通信中使用的相移键控调制扩频信号的扩频解调器。扩频解调器的目的是通过从相关脉冲信号产生具有时间鉴别特性的误差信号来执行跟踪。扩频解调器从相关脉冲信号产生其电平响应于包含在接收信号中的伪噪声信号与参考伪噪声信号之间的相位差而变化的误差信号。从该误差信号产生与接收信号同步的时钟，从而对接收到的信号进行解调。

27. 发明授权

US08728229B2 Cement slurry composition 有权
标题翻译：水泥浆组成
公开(公告)号：US08728229B2
公开(公告)日：2014-05-20
申请号：US13256602
申请日：2009-06-11
申请人： Koji Koyanagi , Toshiharu Kojima , Hotaka Yamamuro
发明人： Koji Koyanagi , Toshiharu Kojima , Hotaka Yamamuro
IPC分类号： C04B24/04
CPC分类号： C09K8/467 , C04B28/02 , C04B40/0039 , C04B2103/0053 , C04B2103/44 , C04B24/005 , C04B2103/404 , C04B24/003 , C04B24/04 , C04B24/20
摘要： The present invention provides a cement slurry composition, containing a hydraulic cement material, (A) a first water-soluble low molecular weight compound and (B) a second water-soluble low molecular weight compound differing from the compound (A), wherein a combination of the compounds (A) and (B) is (I) the compound (A) selected from cationic surfactants and the compound (B) selected from anionic aromatic compounds; or (II) the compound (A) selected from cationic surfactants and the compound (B) selected from brominated compounds, and in the compound (A), a ratio of compounds having a hydrocarbon group of 18 or more carbon atoms is not less than 45% by weight.
摘要翻译：本发明提供含有水硬性水泥材料的水泥浆组合物，（A）第一水溶性低分子量化合物和（B）不同于化合物（A）的第二水溶性低分子量化合物，其中a 化合物（A）和（B）的组合是（I）选自阳离子表面活性剂的化合物（A）和选自阴离子芳族化合物的化合物（B）或（II）选自阳离子表面活性剂的化合物（A）和选自溴化化合物的化合物（B），并且在化合物（A）中，具有18个或更多个碳原子的烃基的化合物的比例不小于 45重量％。

28. 发明授权

US07103107B2 Demodulator, receiver, and communication system 失效
标题翻译：解调器，接收器和通信系统
公开(公告)号：US07103107B2
公开(公告)日：2006-09-05
申请号：US09726533
申请日：2000-12-01
申请人： Mari Matsunaga , Toshiharu Kojima
发明人： Mari Matsunaga , Toshiharu Kojima
IPC分类号： H04L5/12 , H04L23/02 , H04L27/06 , H03D1/00
CPC分类号： H04L27/2332 , H04L25/03178
摘要： A demodulator in a receiver has a multiple symbol differential phase detector which calculates phase differences between a received signal and received signals of 1, 2, . . . , N (Where N is an integer greater than 2) before so as to output the calculated results as N symbol differential phase detected signals. Further, a soft decision sequence estimating unit in this demodulator estimates a transmitted differential phase sequence according to the 1, 2, . . . , N symbol differential phase detected signals using a trellis diagram representing transitions of differential phase states of a transmitted signal and Viterbi algorithm and estimates soft decision demodulated data according to estimated transmitted differential phase sequence and the survival path metrics that transit into each state on the trellis diagram.
摘要翻译：接收机中的解调器具有多符号差分相位检测器，其计算接收信号和1,2的接收信号之间的相位差。。。，其中N（其中N是大于2的整数），以便将计算结果输出为N个符号差分相位检测信号。此外，该解调器中的软判决序列估计单元根据1,2，...估计发送的差分相位序列。。。，N个符号差分相位检测信号，使用表示发射信号和维特比算法的差分相位状态的转变的网格图，并根据估计的传输差分相位序列和过渡到网格中的每个状态的生存路径量度来估计软判决解调数据图。

29. 发明授权

US06650718B1 Timing reproducer and demodulator comprising this 失效
标题翻译：包括此的定时再现器和解调器
公开(公告)号：US06650718B1
公开(公告)日：2003-11-18
申请号：US09926091
申请日：2001-08-28
申请人： Akinori Fujimura , Seiji Okubo , Toshiharu Kojima
发明人： Akinori Fujimura , Seiji Okubo , Toshiharu Kojima
IPC分类号： H04L700
CPC分类号： H04L27/2273 , H04L7/0029 , H04L7/0334 , H04L7/041 , H04L2027/0028 , H04L2027/0036 , H04L2027/0067 , H04L2027/0095
摘要： A timing recovery device and demodulator. An adding device adds together an in-phase component and a quadrature component of a base band signal. A subtracting device subtracts the in-phase component and the quadrature component of the base band signal from each other. Then, the correlation between the added signal and a ½ symbol frequency component generated at the receiver side and the correlation between the subtracted value and the ½ symbol frequency component are calculated. A vector selector compares the added value correlation signal and the subtracted value correlation signal, and selects the larger one of the correlation signals. A timing phase difference calculator then calculates a timing phase difference, using the vector angle indicated by the selected correlation signal.
摘要翻译：定时恢复装置和解调器。加法装置将基带信号的同相分量和正交分量相加在一起。减法装置相减基带信号的同相分量和正交分量。然后，计算相加信号与在接收机侧产生的1/2符号频率分量之间的相关性以及减去的值和1/2符号频率分量之间的相关性。向量选择器比较相加值相关信号和相减值相关信号，并选择较大的一个相关信号。定时相位差计算器然后使用由所选择的相关信号指示的矢量角度来计算定时相位差。

30. 发明授权

US06456672B1 Automatic frequency control communication system 失效
标题翻译：自动频率控制通信系统
公开(公告)号：US06456672B1
公开(公告)日：2002-09-24
申请号：US09066823
申请日：1998-04-28
申请人： Tatsuya Uchiki , Toshiharu Kojima , Hiroyasu Sano , Seiji Okubo , Makoto Miyake
发明人： Tatsuya Uchiki , Toshiharu Kojima , Hiroyasu Sano , Seiji Okubo , Makoto Miyake
IPC分类号： H04L2706
CPC分类号： H04L1/0059 , H03J7/02 , H04B7/06 , H04L1/0054 , H04L1/08 , H04L27/2332
摘要： In a communication system using the time diversity transmission scheme, the communication system provided with the stable automatic frequency control circuit with the wide frequency pull-in range and under low CN ratio transmission is achieved by removing the modulation phase from the received data through the application of the data correlation of the time diversity. The frequency offset in the received signal is compensated as the phase rotator rotates the phase of the received signal, the phase converter converts the phase rotator output into a phase, the serial-to-parallel converter converts the phase converter outputs into serial-to-parallel sequence, the delay units gives a delay to the serial-to-parallel converter output, the phase adder adds the serial-to-parallel converter output to the delay unit output, the multiplier multiplies the phase adder output by a certain value, the integrator integrates the multiplier output, another integrator integrates the integrator output, and the phase rotator controls the phase of the received signal based on the other integrator output.
摘要翻译：在使用时间分集传输方案的通信系统中，具有宽频率拉入范围和低CN比传输的稳定自动频率控制电路的通信系统通过从接收到的数据通过应用去除调制相位来实现的时间分集的数据相关性。接收信号中的频偏被补偿，因为相位旋转器接收信号的相位旋转，相位转换器将相位旋转器输出转换为相位，串并转换器将相位转换器输出转换为串 - 并联序列，延迟单元对串并转换器输出延时，相位加法器将串并转换器输出相加到延迟单元输出，乘法器将相位加法器输出乘以一定值，积分器积分乘法器输出，另一个积分器积分积分器输出，相位旋转器根据其他积分器输出控制接收信号的相位。

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