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    • 3. 发明授权
    • Demodulator and communications system
    • 解调器和通信系统
    • US06601213B1
    • 2003-07-29
    • US09549525
    • 2000-04-14
    • Tatsuya UchikiToshiharu Kojima
    • Tatsuya UchikiToshiharu Kojima
    • H04L102
    • H04L1/0059H04L1/0041H04L1/0042H04L1/0054H04L1/02H04L1/08H04L2027/0048
    • A typical Viterbi decoder having a coherent detection function suffers from degraded performance under certain fading-induced phase shift conditions when used in a time diversity system. This problem is resolved by providing a demodulator for demodulating a data sequence multiplexed by multiplexing a plurality of data sequences of a same content with a time difference inserted therebetween for a time diversity system, which comprises: a phase correction unit 40 for phase correcting the multiplexed data sequence; a diversity combiner for demultiplexing the multiplexed data sequence output from the phase correction unit into a plurality of data sequences, removing the time difference inserted between data sequences, and combining the data sequences; and a Viterbi decoding unit for Viterbi decoding the diversity combined signal from the diversity combiner.
    • 具有相干检测功能的典型维特比解码器在用于时间分集系统的某些衰落诱发相移条件下遭受降级的性能。 该解决方案通过提供一种解调器来解调通过多路复用多个数据序列的数据序列,该数据序列具有相同内容的时间差插入其间的时间分集系统,该时间分集系统包括:相位校正单元40, 数据序列; 分集组合器,用于将从相位校正单元输出的多路复用数据序列解复用为多个数据序列,去除在数据序列之间插入的时差,并组合数据序列; 以及维特比解码单元,用于维特比解码来自分集组合器的分集合并信号。
    • 4. 发明授权
    • Delay lock loop, receiver, and spectrum spreading communication system
    • 延迟锁定环路,接收机和频谱扩展通信系统
    • US06522684B2
    • 2003-02-18
    • US09778938
    • 2001-02-08
    • Seiji OkuboToshiharu KojimaAkinori Fujimura
    • Seiji OkuboToshiharu KojimaAkinori Fujimura
    • H04B1707
    • H04B1/7085
    • In a DLL, in-phase correlation signal and orthogonal correlation signal are squared and adder to generate correlation power. Delays are provided so that the peaks of N number of divided correlation power portions to have coincided timing with each other. Composite correlation power is generated from the respective correlation power portions. A composite error signal of a sample clock is generated by subtracting the composite correlation power from the composite correlation power that has been delayed. A data clock is generated by frequency-dividing the sample clock based upon an acquisition pulse. A sample clock is finally generated based upon the composite error signal that has been latched and noise-removed therefrom in synchronized timing with the data clock that has been delayed.
    • 在DLL中,将相位相关信号和正交相关信号进行平方并产生相关功率。 提供延迟使得N个分割的相关功率部分的峰值彼此具有一致的时序。 从相应的相关功率部分产生复合相关功率。 通过从延迟的复合相关功率中减去复合相关功率来产生采样时钟的复合误差信号。 通过基于采集脉冲对采样时钟进行分频而产生数据时钟。 基于已经被锁定并且与已被延迟的数据时钟同步定时噪声去除的复合误差信号,最终产生采样时钟。