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21. 发明授权

US06509216B2 Memory structure with thin film transistor and method for fabricating the same 有权
公开(公告)号：US06509216B2
公开(公告)日：2003-01-21
申请号：US09801253
申请日：2001-03-07
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L21339
CPC分类号： H01L27/10894 , H01L21/76224 , H01L21/7624 , H01L27/105 , H01L27/10873 , H01L27/1203
摘要： A structure of memory device with thin film transistor is proposed. The structure of the memory device includes a substrate. The substrate has shallow trench isolation structures, a thin film transistor, a memory cell transistor, a memory peripheral transistor, and logic circuit transistor. The shallow trench isolation structures are located in the memory cell region, the logic circuit region, and also on the memory peripheral region to isolate the memory peripheral region from the memory cell region and the logic circuit region. The thin film transistor with a thin film substrate is located above the shallow trench isolation structure at the logic circuit region. A method for fabricating the memory device with thin film transistor is also proposed, where a thin film conductive layer is formed over the substrate at the logic circuit region to serve as the thin film transistor substrate.

22. 发明授权

US06284647B1 Method to improve the uniformity of chemical mechanical polishing 有权
标题翻译：提高化学机械抛光均匀性的方法
公开(公告)号：US06284647B1
公开(公告)日：2001-09-04
申请号：US09216022
申请日：1998-12-16
申请人： Sun-Chieh Chien , Chien-Li Kuo , Tzung-Han Lee , Wei-Wu Liao
发明人： Sun-Chieh Chien , Chien-Li Kuo , Tzung-Han Lee , Wei-Wu Liao
IPC分类号： H01L214163
CPC分类号： H01L21/76229 , Y10S438/926
摘要： A method of enhancing chemical mechanical polishing uniformity is provided. In the fabrication of a shallow trench isolation structure, there are active area regions with different integration formed in a chip. The integration of the active area regions in the chip is computed according circuit designs by a program analysis. One of the active area regions with the highest integration is used as a basis, dummy mesas are formed in the other active area regions to adjust the integration of the chip.
摘要翻译：提供了增强化学机械抛光均匀性的方法。在浅沟槽隔离结构的制造中，在芯片中形成不同积分的有源区域。通过程序分析，根据电路设计计算芯片中有源区域的积分。集成度最高的有源区域之一被用作基础，在其他有源区域中形成虚拟台面以调整芯片的集成。

23. 发明授权

US6008080A Method of making a low power SRAM 失效
标题翻译：制造低功耗SRAM的方法
公开(公告)号：US6008080A
公开(公告)日：1999-12-28
申请号：US975488
申请日：1997-11-21
申请人： Andy Chuang , Tzong-Shien Wu , Sun-Chieh Chien
发明人： Andy Chuang , Tzong-Shien Wu , Sun-Chieh Chien
IPC分类号： H01L21/8244 , H01L27/02 , H01L27/11 , H01L21/70
CPC分类号： H01L27/11 , H01L27/0266 , H01L27/1104 , H01L27/1108
摘要： An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.
摘要翻译：形成具有六个晶体管单元的SRAM。形成下拉晶体管，使得没有砷被注入到下拉晶体管的漏极中，使得下拉晶体管的漏极仅通过磷注入掺杂。下拉晶体管的源极掺杂有磷离子的LDD配置，然后进一步注入砷离子。这可以通过在用于将杂质注入到ESD保护电路的源极/漏极区域中的掩模中提供开口来方便地实现。

24. 发明授权

US5981334A Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US5981334A
公开(公告)日：1999-11-09
申请号：US965326
申请日：1997-11-06
申请人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
发明人： Sun-Chieh Chien , Jason Jenq , C. C. Hsue
IPC分类号： H01L21/02 , H01L21/70 , H01L21/00
CPC分类号： H01L28/82 , H01L28/84 , H01L28/91
摘要： A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode. A dielectric layer is then formed over the lower electrode, and finally an upper electrode layer is formed over the dielectric layer.
摘要翻译：一种用于制造DRAM电容器的方法，其包括在硅衬底上形成具有源极/漏极区域和栅极电极的晶体管; 然后在晶体管上依次形成包括第一绝缘层，第二绝缘层，第三绝缘层和硬掩模层的层叠层; 随后，对硬掩模层进行图案化和蚀刻。此后，在硬掩模层之上形成氧化物层，然后蚀刻这些层的一部分以在氧化物层上形成电容器区域，以及暴露源极/漏极区域的一部分的接触开口。在随后的步骤中，在氧化物层，硬掩模层，接触开口的侧壁和源极/漏极区域的暴露部分之上形成导电层。接下来，使用抛光方法去除氧化物层上方的导电层，然后除去氧化物层以形成下电极。然后在下电极上形成电介质层，最后在电介质层上形成上电极层。

25. 发明授权

US5960280A Method of fabricating a fin/cavity capacitor structure for DRAM cell 失效
标题翻译：制造用于DRAM单元的鳍/腔电容器结构的方法
公开(公告)号：US5960280A
公开(公告)日：1999-09-28
申请号：US975489
申请日：1997-11-21
申请人： Jason Jenq , Sun-Chieh Chien
发明人： Jason Jenq , Sun-Chieh Chien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84
摘要： A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer. A thick polysilicon layer is provided to fill the cavity and then the second, thick polysilicon layer is patterned to laterally define the lower capacitor electrode, preferably leaving portions of the second polysilicon layer extending above the stepped opening and onto surrounding portions of the second insulating layer. The second insulating layer is then removed to expose additional surfaces of the lower capacitor electrode for charge storage. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.
摘要翻译：通过提供转移FET来形成DRAM，在转移FET上方并且靠近转移FET，然后在转移FET的源极/漏极区之一上形成空腔。空腔填充有导体，部分地限定电荷存储电容器的下电极。然后去除腔的部分以暴露电荷存储电容器的下电极的附加电荷存储表面。升高的结构包括设置在转移FET上的厚的平坦化绝缘层。通过在厚的平坦化绝缘层上设置蚀刻掩模形成空腔，其中开口位于第一源极/漏极之上。执行蚀刻以去除第二绝缘层的一部分。提供厚多晶硅层以填充空腔，然后将第二厚多晶硅层图案化以横向限定下电容器电极，优选地使第二多晶硅层的部分在阶梯开口上方延伸到第二绝缘层的周围部分。然后去除第二绝缘层以露出用于电荷存储的下部电容器电极的附加表面。处理继续提供电容器介电层，上电容器电极和位线接触来完成DRAM。

26. 发明授权

US5750438A Method for fabricating a local interconnection structure 失效
标题翻译：制造局部互连结构的方法
公开(公告)号：US5750438A
公开(公告)日：1998-05-12
申请号：US658032
申请日：1996-06-04
申请人： Chen-Chiu Hsue , Sun-Chieh Chien
发明人： Chen-Chiu Hsue , Sun-Chieh Chien
IPC分类号： H01L21/768 , H01L21/283 , H01L21/306
CPC分类号： H01L21/76889
摘要： A local interconnection structure is disclosed. The local interconnection structure is formed on a silicon substrate in which a polysilicon gate and a number of diffusion regions exist. The structure includes a number of metal silicide layers over the substrate, a metal nitride layer over the silicide layers, and a dielectric layer over the nitride layer. The metal nitride layer which electrically connects the diffusion regions and the gate forms the interconnection. The method for fabricating the interconnection structure includes the steps of preparing the silicon substrate, sputtering a metal layer, annealing to form silicide and the nitride layers, depositing the dielectric layer, and patterning the nitride layer and the metal nitride by covering with a mask, etching away portions of both the dielectric layer and metal nitride layer not covered by the mask, and removing the mask after etching.
摘要翻译：公开了局部互连结构。局部互连结构形成在其中存在多晶硅栅极和多个扩散区域的硅衬底上。该结构包括在衬底上的多个金属硅化物层，在硅化物层之上的金属氮化物层，以及氮化物层上方的电介质层。电连接扩散区域和栅极的金属氮化物层形成互连。制造互连结构的方法包括以下步骤：制备硅衬底，溅射金属层，退火以形成硅化物和氮化物层，沉积电介质层，以及用掩模覆盖来对氮化物层和金属氮化物进行图案化，蚀刻除了未被掩模覆盖的电介质层和金属氮化物层的部分，以及蚀刻后去除掩模。

27. 发明授权

US5698458A Multiple well device and process of manufacture 失效
标题翻译：多井设备和制造工艺
公开(公告)号：US5698458A
公开(公告)日：1997-12-16
申请号：US680101
申请日：1996-07-15
申请人： Chen-Chiu Hsue , Sun-Chieh Chien , Chung-Yuan Lee , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Sun-Chieh Chien , Chung-Yuan Lee , Ming-Tzong Yang
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/823892
摘要： A method of manufacture of a semiconductor device comprises forming a silicon dioxide film upon the surface of said device, forming patterns of silicon nitride upon the surface of said silicon dioxide film, ion implanting ions into said substrate adjacent to at least some of said silicon nitride patterns for well regions of a first polarity, forming a mask over said device, and deeply ion implanting with ions of opposite polarity into well regions of opposite polarity.
摘要翻译：一种制造半导体器件的方法包括在所述器件的表面上形成二氧化硅膜，在所述二氧化硅膜的表面上形成氮化硅图案，将离子注入所述衬底中，与所述氮化硅中的至少一些相邻第一极性的阱区的图案，在所述器件上形成掩模，并且将具有相反极性的离子深入离子注入到相反极性的阱区中。

28. 发明授权

US5652160A Method of fabricating a buried contact structure with WSi.sub.x sidewall spacers 失效
标题翻译：用WSix侧壁间隔件制造掩埋接触结构的方法
公开(公告)号：US5652160A
公开(公告)日：1997-07-29
申请号：US613092
申请日：1996-03-08
申请人： Jengping Lin , Sun-Chieh Chien
发明人： Jengping Lin , Sun-Chieh Chien
IPC分类号： H01L21/74 , H01L23/48 , H01L21/335
CPC分类号： H01L21/28525
摘要： A method of forming WSi.sub.x sidewall spacers as an etching stop in the fabrication process of a buried contact. After a gate dielectric layer and a first conducting layer are formed over a substrate, an opening is formed by etching through the gate dielectric layer and first conducting layer. WSi.sub.x sidewall spacers are thereafter formed on the sidewalls of the opening. Then, a second conducting layer is deposited onto the overall surface as well as being connected to the substrate via the opening. When the second and first conducting layers are patterned and etched to form a gate electrode and an interconnect layer, the WSi.sub.x acts as the etching stop to prevent the formation of ditches in the substrate.
摘要翻译：在掩埋接触的制造工艺中形成WSix侧壁间隔物作为蚀刻停止件的方法。在基板之上形成栅极介电层和第一导电层之后，通过蚀刻通过栅极介电层和第一导电层形成开口。此后在开口的侧壁上形成WSix侧壁间隔物。然后，第二导电层沉积在整个表面上，并且经由开口连接到基板。当第二导电层和第一导电层被图案化和蚀刻以形成栅电极和互连层时，WSix充当蚀刻停止件以防止在衬底中形成沟槽。

29. 发明授权

US5612239A Use of oxide spacers formed by liquid phase deposition 失效
标题翻译：使用通过液相沉积形成的氧化物间隔物
公开(公告)号：US5612239A
公开(公告)日：1997-03-18
申请号：US519069
申请日：1995-08-24
申请人： Jengping Lin , Sun-Chieh Chien
发明人： Jengping Lin , Sun-Chieh Chien
IPC分类号： H01L21/316 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/316
摘要： A process for manufacturing an LDD type of FET, based on the salicide process, is described. Said process does not lead to short circuits between the drain region and and the main body of the FET through the buried contact. The process is based on the use of Liquid Phase Deposition (LPD) as the method for growing the oxide layer from which the spacers are formed. Since oxide layers formed through LPD will deposit preferentially on silicon and silicon oxide surfaces relative to photoresist surfaces, the areas in which the LPD layer forms are readily controlled. This feature allows the buried contact layer to be replaced by an extended drain region which can be connected to other parts of the integrated circuit (by the salicide process) without the danger of shorting paths being formed therein.
摘要翻译：描述了基于自对准硅化物工艺制造LDD型FET的工艺。所述工艺不会通过埋入触点而导致漏极区域和FET主体之间的短路。该方法基于使用液相沉积（LPD）作为生长形成间隔物的氧化物层的方法。由于通过LPD形成的氧化物层相对于光致抗蚀剂表面优先沉积在硅和氧化硅表面上，因此容易控制LPD层形成的区域。该特征允许掩埋接触层被延伸的漏极区域替代，该漏极区域可以连接到集成电路的其它部分（通过自对准硅化物工艺），而不会在其中形成短路路径的危险。

30. 发明授权

US5554560A Method for forming a planar field oxide (fox) on substrates for integrated circuit 失效
标题翻译：在集成电路基板上形成平面场氧化物（fox）的方法
公开(公告)号：US5554560A
公开(公告)日：1996-09-10
申请号：US315772
申请日：1994-09-30
申请人： Chen-Chiu Hsue , Sun-Chieh Chien , Ming-Hua Liu
发明人： Chen-Chiu Hsue , Sun-Chieh Chien , Ming-Hua Liu
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/31055
摘要： An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.
摘要翻译：实现了在硅衬底上制造平面场氧化物结构的改进方法。该方法包括通过使用硅的LOCal氧化（LOCOS）工艺形成场氧化物，其中器件区域被氮化硅层防止氧化。使用诸如旋涂玻璃（SOG）或抗反射涂层（ARC）层的牺牲调平层填充氮化硅和场氧化物结构之间的间隙，并使基板表面更平坦。然后通过等离子体蚀刻非选择性地蚀刻流平层，以平坦化在衬底表面上方延伸的场氧化物的部分。该方法不需要在硅衬底中蚀刻凹槽，因此具有一定的可靠性和成本优点。

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