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21. 发明授权

US07352636B2 Circuit and method for generating boosted voltage in semiconductor memory device 失效
标题翻译：用于在半导体存储器件中产生升高电压的电路和方法
公开(公告)号：US07352636B2
公开(公告)日：2008-04-01
申请号：US11313722
申请日：2005-12-22
申请人： Soo-bong Chang , Chi-wook Kim
发明人： Soo-bong Chang , Chi-wook Kim
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C11/406 , G11C11/4074 , G11C2211/4065
摘要： In a boosted voltage generating circuit of a semiconductor memory device, an active kicker drive signal generating circuit generates an active kicker drive signal having a first pulse duration in response to a row active command, and generates the active kicker drive signal having a second pulse duration in response to a refresh command. An active kicker circuit is responsive to the active kicker drive signal to generate the boosted voltage. The second pulse duration may be greater than the first pulse duration, which makes it possible to improve the pumping efficiency of the boosted voltage in a refresh operation.
摘要翻译：在半导体存储器件的升压电压产生电路中，有源icker驱动信号发生电路响应于行有效命令产生具有第一脉冲持续时间的有效icker驱动信号，并产生具有第二脉冲持续时间响应刷新命令。有源激光电路响应于激活的激光驱动信号以产生升压电压。第二脉冲持续时间可以大于第一脉冲持续时间，这使得可以在刷新操作中提高升压电压的泵送效率。

22. 发明申请

US20070041256A1 LAYOUT FOR EQUALIZER AND DATA LINE SENSE AMPLIFIER EMPLOYED IN A HIGH SPEED MEMORY DEVICE 有权
标题翻译：在高速存储器件中使用的均衡器和数据线检测放大器的布局
公开(公告)号：US20070041256A1
公开(公告)日：2007-02-22
申请号：US11383727
申请日：2006-05-16
申请人： Soo-Bong CHANG , Chi-Wook KIM
发明人： Soo-Bong CHANG , Chi-Wook KIM
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/062 , G11C11/4091 , G11C11/4093
摘要： A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.
摘要翻译：存储器件包括存储单元阵列块，存储单元阵列块，与沿着存储单元的字线排列的方向布置的存储单元阵列块相邻的字线驱动块，设置有存储单元阵列块的读出放大器块在布置存储单元的位线的方向上，设置在字线驱动块和读出放大器块的交叉点处的连接块，用于均衡一对本地数据线的均衡器，均衡器配置在一起块和本地数据线读出放大器，其被配置为感测和放大一对本地数据线上的信号，并且具有布置在连接块中的第一类型的晶体管和布置在读出放大器块中的第二类型的晶体管。

23. 发明授权

US07075849B2 Semiconductor memory device and layout method thereof 失效
标题翻译：半导体存储器件及其布局方法
公开(公告)号：US07075849B2
公开(公告)日：2006-07-11
申请号：US10786855
申请日：2004-02-24
申请人： Soo-Bong Chang , Jung-Hwa Lee , Chi-Wook Kim , Byong-Mo Moon
发明人： Soo-Bong Chang , Jung-Hwa Lee , Chi-Wook Kim , Byong-Mo Moon
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/14
摘要： Embodiments of the invention provide drivers from active internal voltage generating circuits on both sides of the internal voltage generating lines, therefore a voltage level of the internal voltage generating lines can quickly and uniformly reach a desired internal voltage level. Other embodiments of the invention are described in the claims.
摘要翻译：本发明的实施例提供了内部电压发生线两侧的有源内部电压产生电路的驱动器，因此内部电压发生线的电压电平可以快速均匀地达到期望的内部电压电平。在权利要求中描述了本发明的其它实施例。

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