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21. 发明申请

US20100091601A1 CIRCUIT AND METHODS FOR ELIMINATING SKEW BETWEEN SIGNALS IN SEMICODUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于消除半导体集成电路中信号之间的差异的电路和方法
公开(公告)号：US20100091601A1
公开(公告)日：2010-04-15
申请号：US12635751
申请日：2009-12-11
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-Jin Jang
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.
摘要翻译：一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移的半导体存储器件。

22. 发明申请

US20080186075A1 Level shifter of semiconductor device and method for controlling duty ratio in the device 有权
标题翻译：半导体器件的电平移位器和装置中占空比的控制方法
公开(公告)号：US20080186075A1
公开(公告)日：2008-08-07
申请号：US11986841
申请日：2007-11-27
申请人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
发明人： Jin-Gook Kim , Seung-Jun Bae , Dae-Hyun Chung
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/017
摘要： A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third and fourth NMOS transistors having sources connected to drains of the first and second NMOS transistors and gates to which the power supply voltage is applied; and a voltage controlled delay unit for receiving an input signal applied to a gate of the first NMOS transistor, inverting a level of the input signal, determining whether a voltage of an inverted input signal should be charged in response to a voltage control signal, outputting the voltage of the inverted input signal of which delay time is controlled, and applying the inverted input signal to a gate of the second NMOS transistor.
摘要翻译：提供半导体器件的电平移位器和控制占空比的方法。电平移位器包括具有施加电源电压的源的第一和第二PMOS晶体管，具有施加接地电压的源的第一和第二NMOS晶体管，具有连接到第一和第二漏极的漏极的源的第三和第四NMOS晶体管施加电源电压的NMOS晶体管和栅极; 以及电压控制延迟单元，用于接收施加到第一NMOS晶体管的栅极的输入信号，反相输入信号的电平，确定反相输入信号的电压是否应当响应于电压控制信号而被充电，输出控制延迟时间的反相输入信号的电压，并将反相输入信号施加到第二NMOS晶体管的栅极。

23. 发明申请

US20080130811A1 CIRCUIT AND METHOD FOR REMOVING SKEW IN DATA TRANSMITTING/RECEIVING SYSTEM 有权
标题翻译：用于在数据发送/接收系统中移除数据的电路和方法
公开(公告)号：US20080130811A1
公开(公告)日：2008-06-05
申请号：US12029518
申请日：2008-02-12
申请人： Seung-Jun Bae , Kwang-Il Park , Seong-jin Jang
发明人： Seung-Jun Bae , Kwang-Il Park , Seong-jin Jang
IPC分类号： H04L7/00 , G11B20/20
CPC分类号： G11C7/22 , G11C5/063 , G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/222
摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.
摘要翻译：数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。定时控制单元通过发送端接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与施加到发送输出单元的发送采样时钟信号之间的定时结果。可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

24. 发明申请

US20080100357A1 Delay locked loop circuit, semiconductor device having the same and method of controlling the same 有权
标题翻译：延迟锁定环电路，具有相同的半导体器件及其控制方法
公开(公告)号：US20080100357A1
公开(公告)日：2008-05-01
申请号：US11978636
申请日：2007-10-30
申请人： Seung-Jun Bae
发明人： Seung-Jun Bae
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0812 , H03L7/0818 , H03L7/087 , H03L7/10
摘要： A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.
摘要翻译：延迟锁定环（DLL）电路包括基本循环，粗循环，延迟模型和精细循环。至少部分地基于输入时钟信号，反馈时钟信号和精细回路输出信号，基本回路产生多个第一时钟信号。第一时钟信号分别具有相位差。至少部分地基于输入时钟信号，反馈时钟信号和第一时钟信号，粗略回路产生多个输出时钟信号。多个输出时钟信号分别具有相位差。延迟模型通过将输出时钟信号之一延迟第一时间段来产生反馈时钟信号。至少部分地基于输入时钟信号和反馈时钟信号，精细循环产生精细环路输出信号。

25. 发明申请

US20070242508A1 Low power balance code using data bus inversion 有权
标题翻译：低功耗平衡码使用数据总线反演
公开(公告)号：US20070242508A1
公开(公告)日：2007-10-18
申请号：US11730795
申请日：2007-04-04
申请人： Seung-Jun Bae
发明人： Seung-Jun Bae
IPC分类号： G11C11/34
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1048 , G11C11/406
摘要： A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.
摘要翻译：用于减少刷新存储器所需的功率消耗的方法和装置可以接收已经使用数据总线反转（DBI）编码的数据，DBI数据具有在零和DBI最大值之间的不同情况下的零个数之间的第一增量，余额对DBI数据进行编码以平衡DBI数据上的零数，并且输出具有大于零且小于或等于DBI最大值的最小数量和等于最小值的最大数量的不同情况下的零个数的数据数字加上第二个delta，第二个delta小于第一个delta。

26. 发明申请

US20070206428A1 HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
标题翻译：高速相位调整数据速率（QDR）收发器及其方法
公开(公告)号：US20070206428A1
公开(公告)日：2007-09-06
申请号：US11612800
申请日：2006-12-19
申请人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
发明人： Seung-Jun Bae , Seong-Jin Jang , Kwang-II Park , Sang-Woong Shin , Ho-Young Song
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.
摘要翻译：提供了一种高速双倍或正交数据速率接口半导体器件及其方法。用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和第二组（字节）数据。发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

27. 发明授权

US07161398B2 VCDL-based dual loop DLL having infinite phase shift function 失效
标题翻译：基于VCDL的双循环DLL具有无限相移功能
公开(公告)号：US07161398B2
公开(公告)日：2007-01-09
申请号：US11142698
申请日：2005-06-01
申请人： Hong June Park , Seung Jun Bae
发明人： Hong June Park , Seung Jun Bae
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0814
摘要： Provided is a dual loop DLL for generating an internal clock signal synchronized with an external clock, which includes a reference DLL receiving a reference clock and generating a plurality of phase clock signals having a first phase difference, a coarse loop selecting one of the phase clock signals and generating first through third digital codes to allow the internal clock signal to have a phase difference smaller than a second phase difference with respect to the external clock, and a fine loop selecting two of the phase clock signals and synchronizing the internal clock signal with the external clock, in response to the first through third digital codes.
摘要翻译：提供了一种用于产生与外部时钟同步的内部时钟信号的双循环DLL，其包括接收参考时钟并产生具有第一相位差的多个相位时钟信号的参考DLL，粗略选择相位时钟之一信号并产生第一至第三数字代码，以允许内部时钟信号相对于外部时钟具有小于第二相位差的相位差，以及选择两个相位时钟信号并使内部时钟信号与外部时钟，响应于第一到第三数字代码。

28. 发明授权

US08780668B2 Semiconductor device, a parallel interface system and methods thereof 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US08780668B2
公开(公告)日：2014-07-15
申请号：US13483719
申请日：2012-05-30
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.
摘要翻译：存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

29. 发明授权

US08631266B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08631266B2
公开(公告)日：2014-01-14
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

30. 发明授权

US08390317B2 Bidirectional equalizer with CMOS inductive bias circuit 有权
标题翻译：带CMOS感应偏置电路的双向均衡器
公开(公告)号：US08390317B2
公开(公告)日：2013-03-05
申请号：US12832212
申请日：2010-07-08
申请人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-sik Kim , Sang-hyup Kwak
IPC分类号： H03K19/0175
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1057 , G11C7/1084 , H03K19/018521
摘要： An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency.
摘要翻译：描述了一种用于传送数据的集成电路（IC）装置，系统和相关方法。 IC器件包括：数据端口，被配置为向通道提供输出数据并从所述通道接收输入数据;阻抗匹配电路，连接到所述数据端口，并且被配置为当所述输出数据被发送时作为输出驱动器电路工作，并且作为管芯端接接收输入数据时的电路以及与阻抗匹配电路并联连接到数据端口的有源感应偏置电路，并且被配置为在输出数据作为功能的传输期间调整数据端口到通道的阻抗的输出数据频率，并根据输入数据频率调整输入数据接收期间数据端口到通道的阻抗。

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