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21. 发明申请

US20060218373A1 Processor and method of indirect register read and write operations 有权
标题翻译：间接寄存器读写操作的处理器和方法
公开(公告)号：US20060218373A1
公开(公告)日：2006-09-28
申请号：US11089619
申请日：2005-03-24
申请人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
发明人： Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
IPC分类号： G06F9/34
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译：处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值，以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储基于第二寄存器值将第一寄存器值输入到第三寄存器中。

22. 发明授权

US08688761B2 Arithmetic logic and shifting device for use in a processor 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US08688761B2
公开(公告)日：2014-04-01
申请号：US13314530
申请日：2011-12-08
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F7/00 , G06F15/00 , G06F7/38 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

23. 发明授权

US08195916B2 Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode 失效
标题翻译：将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法
公开(公告)号：US08195916B2
公开(公告)日：2012-06-05
申请号：US12397438
申请日：2009-03-04
申请人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
发明人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

24. 发明授权

US08099448B2 Arithmetic logic and shifting device for use in a processor 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US08099448B2
公开(公告)日：2012-01-17
申请号：US11266076
申请日：2005-11-02
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F7/00 , G06F15/00 , G06F7/38 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

25. 发明授权

US07849466B2 Controlling execution mode of program threads by applying a mask to a control register in a multi-threaded processor 有权
标题翻译：通过对多线程处理器中的控制寄存器应用掩码来控制程序线程的执行模式
公开(公告)号：US07849466B2
公开(公告)日：2010-12-07
申请号：US11180017
申请日：2005-07-12
申请人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
发明人： Lucian Codrescu , Donald Robert Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William C. Anderson , Sujat Jamil
IPC分类号： G06F9/46 , G06F9/45 , G06F15/00
CPC分类号： G06F9/3851 , G06F1/3228 , G06F1/3243 , G06F9/30181 , G06F9/30189 , G06F9/3853 , G06F9/4843 , Y02D10/152 , Y02D10/24
摘要： A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.
摘要翻译：公开了一种多线程处理器设备，并且包括被配置为执行多个可执行程序线程和模式控制寄存器的处理器。模式控制寄存器包括用于控制多个可执行程序线程中的第一个的第一执行模式的第一数据字段和用于控制多个可执行程序线程中的第二个可执行程序线程的第二执行模式的第二数据字段。在特定实施例中，第一执行模式是运行模式，第二执行模式是低功率模式。

26. 发明授权

US07590824B2 Mixed superscalar and VLIW instruction issuing and processing method and system 有权
标题翻译：混合超标量和VLIW指令发布和处理方法和系统
公开(公告)号：US07590824B2
公开(公告)日：2009-09-15
申请号：US11093375
申请日：2005-03-29
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。该系列可执行指令通过各种指令依赖关联。该方法和系统进一步标识列出多个并行可执行指令的混合指令。一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。然后，根据所述各种指令依赖性，串行执行指令被串行执行。

27. 发明申请

US20070016759A1 System and method of controlling multiple program threads within a multithreaded processor 有权
标题翻译：在多线程处理器中控制多个程序线程的系统和方法
公开(公告)号：US20070016759A1
公开(公告)日：2007-01-18
申请号：US11180017
申请日：2005-07-12
申请人： Lucian Codrescu , Donald Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William Anderson , Sujat Jamil
发明人： Lucian Codrescu , Donald Padgett , Erich Plondke , Taylor Simpson , Muhammad Ahmed , William Anderson , Sujat Jamil
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F1/3228 , G06F1/3243 , G06F9/30181 , G06F9/30189 , G06F9/3853 , G06F9/4843 , Y02D10/152 , Y02D10/24
摘要： A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.
摘要翻译：公开了一种多线程处理器设备，并且包括被配置为执行多个可执行程序线程和模式控制寄存器的处理器。模式控制寄存器包括用于控制多个可执行程序线程中的第一个的第一执行模式的第一数据字段和用于控制多个可执行程序线程中的第二个可执行程序线程的第二执行模式的第二数据字段。在特定实施例中，第一执行模式是运行模式，第二执行模式是低功率模式。

28. 发明申请

US20060218379A1 Method and system for encoding variable length packets with variable instruction sizes 有权
公开(公告)号：US20060218379A1
公开(公告)日：2006-09-28
申请号：US11088607
申请日：2005-03-23
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , William Anderson
IPC分类号： G06F9/40
CPC分类号： G06F9/30149 , G06F9/3853
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.

29. 发明申请

US20060206902A1 Variable interleaved multithreaded processor method and system 审中-公开
标题翻译：可变交错多线程处理器方法和系统
公开(公告)号：US20060206902A1
公开(公告)日：2006-09-14
申请号：US11080239
申请日：2005-03-14
申请人： Sujat Jamil , Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
发明人： Sujat Jamil , Erich Plondke , Lucian Codrescu , Muhammad Ahmed , William Anderson
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The triggering event is variably and dynamically determined to optimize multithreaded processor performance. The triggering event may be a dynamically determined number of processor cycles, the number being determined to optimize the performance of the multithreaded processor, or a variably and dynamically determined event, such as a cache or instruction miss.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。多线程处理器处理通过与多线程处理器相关联的多个处理器管线操作的多个线程，并且预先确定用于多线程处理器从第一线程切换到第二线程的触发事件。触发事件是可变和动态的，以优化多线程处理器性能。触发事件可以是动态确定的处理器周期数，被确定为优化多线程处理器的性能的数量，或可变和动态确定的事件，例如高速缓存或指令未命中。

30. 发明授权

US08713286B2 Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
标题翻译：为交错多线程环境中的数字信号处理器注册文件
公开(公告)号：US08713286B2
公开(公告)日：2014-04-29
申请号：US11115916
申请日：2005-04-26
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F7/57
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

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