专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050237803A1 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US20050237803A1
公开(公告)日：2005-10-27
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

22. 发明申请

US20050095769A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050095769A1
公开(公告)日：2005-05-05
申请号：US10499667
申请日：2002-02-28
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C16/04 , G11C16/24 , G11C16/34 , H01L21/8238
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

23. 发明授权

US06721207B2 Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches 有权
标题翻译：非易失性存储器系统，包括用于控制包括存储器单元和数据锁存器的非易失性器件的写入，读取和存储和输出操作的控制装置
公开(公告)号：US06721207B2
公开(公告)日：2004-04-13
申请号：US10211342
申请日：2002-08-05
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G51C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.
摘要翻译：非易失性存储器系统设置有控制设备和非易失性存储器设备，每个包括存储器单元和数据锁存器。控制装置向非易失性存储装置提供包括写入命令以及第一和第二读取命令的命令。当控制装置向写入命令提供写入地址信息和用于存储在非易失性存储器件中的数据时，它将数据存储到数据锁存器，然后存储到存储器单元，然后验证存储器。当控制装置向读取地址信息提供第一读取命令时，非易失性存储器件将存储在存储器单元中的数据读取到数据锁存器，然后将数据锁存器中的数据输出到控制装置。当控制装置提供第二读取命令时，非易失性存储装置将数据锁存器中的数据输出到控制装置。

24. 发明授权

US06507520B2 Nonvolatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US06507520B2
公开(公告)日：2003-01-14
申请号：US10011723
申请日：2001-12-11
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.
摘要翻译：外部提供的程序数据被锁存在数据锁存电路DLL和DLR中。在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

25. 发明授权

US06456526B2 Non-volatile memory device operation in response to two different types of read commands and a write command which includes write verification 有权
标题翻译：响应于两种不同类型的读取命令的非易失性存储器件操作和包括写入验证的写入命令
公开(公告)号：US06456526B2
公开(公告)日：2002-09-24
申请号：US09820894
申请日：2001-03-30
申请人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
发明人： Tetsuya Tsujikawa , Atsushi Nozoe , Michitaro Kanamitsu , Shoji Kubono , Eiji Yamamoto , Ken Matsubara
IPC分类号： G11C1604
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/3463 , G11C2211/5642
摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.
摘要翻译：具有多个存储单元和控制电路的非易失性存储器件。控制电路从设备外部接收操作命令，并根据命令控制设备的操作。命令包括读命令和写命令。在读命令中，控制电路读取存储单元中的数据并将其输出。在写命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。控制电路提供指示数据写入是成功还是失败的状态信息。

26. 发明授权

US6078519A Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell 有权
公开(公告)号：US6078519A
公开(公告)日：2000-06-20
申请号：US317976
申请日：1999-05-25
申请人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
发明人： Michitaro Kanamitsu , Tetsuya Tsujikawa , Toshinori Harada , Hiroaki Kotani , Shoji Kubono , Atsushi Nozoe , Takayuki Yoshitake
IPC分类号： G11C16/02 , G11C11/34 , G11C16/00 , G11C16/04 , G11C29/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2211/5642
摘要： Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.

27. 发明授权

US5467315A Semiconductor memory device facilitated with plural self-refresh modes 失效
标题翻译：具有多个自刷新模式的半导体存储器件
公开(公告)号：US5467315A
公开(公告)日：1995-11-14
申请号：US234414
申请日：1994-04-28
申请人： Takeshi Kajimoto , Yutaka Shimbo , Katsuyuki Sato , Masahiro Ogata , Kanehide Kenmizaki , Shouji Kubono , Nobuo Kato , Kiichi Manita , Michitaro Kanamitsu
发明人： Takeshi Kajimoto , Yutaka Shimbo , Katsuyuki Sato , Masahiro Ogata , Kanehide Kenmizaki , Shouji Kubono , Nobuo Kato , Kiichi Manita , Michitaro Kanamitsu
IPC分类号： G01R31/26 , G01R31/28 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4093 , G11C29/00 , G11C29/02 , G11C29/14 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H03K3/037 , H03K19/096 , G11C7/00
CPC分类号： G11C29/027 , G11C11/406 , G11C11/4093 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2029/5004
摘要： The semiconductor memory is facilitated with control circuitry for effecting plural self-refresh modes having respectively different refresh periods. The plural self-refresh modes are typified by a PS (pseudo) refresh mode which is applied when the memory is in the nonselected state for a comparatively long period of time, such as in the state in which memory backup is being facilitated, and by a VS (virtual) refresh mode in which the refreshing operation of the memory cells is effected intermittently during the intervals of memory accessings. The pseudo refresh mode has a longer refresh time period than the virtual refresh mode. The control circuitry also has counter circuits for the generating of refresh address signals in accordance with a first timing signal indicative of a pseudo refresh mode and a second timing signal indicative of a virtual refresh mode, the latter timing signal being a higher frequency signal. Such availability of plural self-refresh modes becomes particularly advantageous when considering consumption of the back-up power for maintaining the IC memory device versus stability of stored data. While the consumption of the back-up power for maintaining the device would be relatively lower under one of the self-refresh modes, namely, the PS (pseudo) refresh mode, the stability of data stored would, however, be greater under another self-refresh mode, namely, the VS (virtual) refresh mode.
摘要翻译：利用用于实现分别具有不同刷新周期的多个自刷新模式的控制电路来促进半导体存储器。多个自刷新模式以PS（伪）刷新模式为代表，当存储器处于非选择状态较长时间段时，例如在便于存储器备份的状态下，以及由在存储器访问的间隔期间间歇地执行存储器单元的刷新操作的VS（虚拟）刷新模式。伪刷新模式具有比虚拟刷新模式更长的刷新时间段。控制电路还具有用于根据指示伪刷新模式的第一定时信号和指示虚拟刷新模式的第二定时信号产生刷新地址信号的计数器电路，后一定时信号是较高频率信号。当考虑用于维持IC存储器件的备用电源与存储的数据的稳定性的消耗时，这种多重自刷新模式的可用性变得特别有利。虽然在自刷新模式之一（即PS）（伪）刷新模式下，用于维持设备的备份功率的消耗将相对较低，但是存储的数据的稳定性在另一个自身下将更大 - 刷新模式，即VS（虚拟）刷新模式。

28. 发明申请

US20080266937A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080266937A1
公开(公告)日：2008-10-30
申请号：US12109339
申请日：2008-04-24
申请人： Masayuki HIRAYAMA , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
发明人： Masayuki HIRAYAMA , Masami Hasegawa , Michitaro Kanamitsu , Yayoi Hayashi , Naoyuki Anan
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.
摘要翻译：本发明的半导体器件具有在多个字线和多个互补位线的交叉部分设置有多个CMOS静态存储单元的存储单元阵列。在存储单元阵列中，开关MOSFET在与第一操作模式不同的第一操作模式和第二操作模式中处于断开状态，并且具有第一导电类型和第二导电类型的MOSFET，其具有在构成构成多个静态存储单元的第一和第二CMOS反相器电路的第一导电型MOSFET的源极连接到的第一源极线和与第一源极线对应的第一电源线之间并联设置二极管配置。构成第一和第二CMOS反相器电路的第二导电型MOSFET的源极连接的第二源极线连接到与其对应的第二电源线。

29. 发明授权

US07095657B2 Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array 有权
标题翻译：能够在存储器阵列中实现优化的擦除操作的非易失性半导体存储器件
公开(公告)号：US07095657B2
公开(公告)日：2006-08-22
申请号：US11224964
申请日：2005-09-14
申请人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
发明人： Yoshinori Takase , Hideaki Kurata , Keiichi Yoshida , Ken Matsubara , Michitaro Kanamitsu , Shinji Yuasa
IPC分类号： G11C7/10
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.
摘要翻译：一种非易失性半导体存储器件，其能够在存储器阵列配置中实现优化的擦除操作，其中多个页面对应于并连接到多个字线中的每一个并且更高的擦除操作速度。在闪速存储器中，通过擦除多个任意选择的多个页面的擦除方法进行擦除操作。在两页擦除模式中，按顺序执行页擦除，页预擦除验证，页重写处理，页预重写验证和页上限确定处理。该方法特别地实现（1）通过仅在擦除页面中的任意一个偶数页或奇数页上执行擦除验证，以便考虑到擦除特性的变化来将擦除验证次数抑制到最小，以及（2）防止擦除上端的错误判断，因为不必每次重写验证来设置要重写的存储单元，通过逐页连续执行重写处理。

30. 发明授权

US07072225B2 Nonvolatile memory and method of programming the same memory 失效
公开(公告)号：US07072225B2
公开(公告)日：2006-07-04
申请号：US11168331
申请日：2005-06-29
申请人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
发明人： Yoshinori Takase , Shoji Kubono , Michitaro Kanamitsu , Atsushi Nozoe , Keiichi Yoshida , Hideaki Kurata
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/12
摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式