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21. 发明授权

US07480759B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 失效
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07480759B2
公开(公告)日：2009-01-20
申请号：US11772922
申请日：2007-07-03
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

22. 发明授权

US07451273B2 System, method and storage medium for providing data caching and data compression in a memory subsystem 有权
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US07451273B2
公开(公告)日：2008-11-11
申请号：US11780048
申请日：2007-07-19
申请人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
发明人： Kevin C. Gower , Mark W. Kellogg , Warren E. Maule , Thomas B. Smith, III , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

23. 发明授权

US07380179B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US07380179B2
公开(公告)日：2008-05-27
申请号：US11406669
申请日：2006-04-20
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David T. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David T. Perlman
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。模块上的冗余联系人可防止出现单点故障。

24. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

25. 发明授权

US06385685B1 Memory card utilizing two wire bus 失效
公开(公告)号：US06385685B1
公开(公告)日：2002-05-07
申请号：US09833871
申请日：2001-04-12
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
IPC分类号： G06F1338
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

26. 发明授权

US6070217A High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance 失效
标题翻译：具有串行总线开关的高密度存储器模块响应于连接的RAM组的读/写选择状态而被使能，以提高数据总线性能
公开(公告)号：US6070217A
公开(公告)日：2000-05-30
申请号：US76265
申请日：1998-05-12
申请人： Brian J. Connolly , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Brian J. Connolly , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G11C5/00 , G06F13/16 , G06F13/40 , G11C11/401 , H01L27/10 , G06F13/00 , G06F12/00 , G06F12/06
CPC分类号： G06F13/4068
摘要： Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise. The RAM is Fast Page Mode (FPM) and Extended Data Output (EDO) or Synchronous DRAM (SDRAM).
摘要翻译：在具有多个DRAM的高密度模块上的数据线负载被最小化，从而可以增加其他有限密度的系统的最大存储器密度，而不会由于数据线容性负载而导致随后的性能下降。首先，单列或双列直插式内存模块（SIMM或DIMM）包括在线总线开关。总线开关位于SIMM或DIMM模块选项卡（系统）和随机存取存储设备（RAM）之间，并且根据RAM的读/写状态，处于高阻抗（关闭）或活动状态。当处于高阻态时，模块的有效负载是位开关器件的有效负载。用于确定读/写状态的逻辑可以被嵌入到专用集成电路（ASIC）中，该专用集成电路监视总线活动并控制总线开关的激活，由存储器控制器提供或由RAM本身产生。当RAM执行读或写操作时，总线开关处于活动状态。 RAM是快速页面模式（FPM）和扩展数据输出（EDO）或同步DRAM（SDRAM）。

27. 发明授权

US5969997A Narrow data width DRAM with low latency page-hit operations 失效
标题翻译：狭窄的数据宽度DRAM，具有低延迟页命中操作
公开(公告)号：US5969997A
公开(公告)日：1999-10-19
申请号：US942825
申请日：1997-10-02
申请人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
发明人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C11/409 , G11C11/407
摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
摘要翻译：高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率潜伏。因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。

28. 发明授权

US5757712A Memory modules with voltage regulation and level translation 失效
标题翻译：具有电压调节和电平转换的内存模块
公开(公告)号：US5757712A
公开(公告)日：1998-05-26
申请号：US678867
申请日：1996-07-12
申请人： Johann W. Nagel , Mark W. Kellogg , Bruce G. Hazelzet
发明人： Johann W. Nagel , Mark W. Kellogg , Bruce G. Hazelzet
IPC分类号： G11C5/00 , G11C5/14 , G11C7/10 , H05K1/02
CPC分类号： H05K1/0256 , G11C5/147 , G11C7/1006 , H05K1/0262 , H05K2201/10166 , H05K2201/10196 , H05K2201/10689
摘要： Low voltage DRAMs are used on higher voltage memory modules in a way that requires no modification of the DRAMs. "Bus switch" technology and compact low voltage regulators are used at the module level. The low voltage regulator provides a lowered, regulated voltage to DRAMs. The bus switches are used at the inputs and outputs of the DRAMs and effectively protect the DRAM circuitry from voltage swings that could otherwise be damaging.
摘要翻译：低电压DRAM以不需要修改DRAM的方式用于高电压存储器模块。在模块级使用“总线开关”技术和紧凑型低压调节器。低电压调节器为DRAM提供降低的稳压电压。总线开关用于DRAM的输入和输出，并有效地保护DRAM电路免受可能会造成损害的电压摆幅。

29. 发明授权

US08296541B2 Memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的内存子系统
公开(公告)号：US08296541B2
公开(公告)日：2012-10-23
申请号：US12369037
申请日：2009-02-11
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.
摘要翻译：提供具有包括一个或多个存储器模块，存储器控制器和一个或多个存储器总线的位置读取数据延迟的存储器子系统。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过存储器总线相互连接。

30. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

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