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21. 发明申请

US20100039852A1 Dynamic Memory Cell Methods 有权
标题翻译：动态记忆单元方法
公开(公告)号：US20100039852A1
公开(公告)日：2010-02-18
申请号：US12542802
申请日：2009-08-18
申请人： Wing K. Luk , Jin Cai
发明人： Wing K. Luk , Jin Cai
IPC分类号： G11C11/24 , H01L21/8242 , G11C7/00
CPC分类号： G11C11/4097 , G11C7/18 , G11C8/16 , G11C11/405 , H01L21/28079 , H01L21/84 , H01L27/10873 , H01L29/495
摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.
摘要翻译：公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

22. 发明申请

US20090321831A1 PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION 有权
标题翻译：具有金属化源侧HALO区域的部分沉积SOI场效应晶体管
公开(公告)号：US20090321831A1
公开(公告)日：2009-12-31
申请号：US12554344
申请日：2009-09-04
申请人： Jin Cai , Wilfried Haensch , Amlan Majumdar
发明人： Jin Cai , Wilfried Haensch , Amlan Majumdar
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/458 , H01L29/66772 , H01L29/78612 , H01L29/78624
摘要： Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.
摘要翻译：源极和漏极延伸区域和源极侧卤素区域和漏极侧晕圈形成在与SOI衬底上的栅极堆叠对准的顶部半导体层中。通过成角度的离子注入，在顶部半导体层中不均匀地形成深源区和深漏区。深源区域远离至少间隔物的外缘之一偏离以暴露半导体衬底的表面上的源延伸区域。源金属半导体合金通过使金属层与深源区，源极延伸区和源极侧晕区的一部分反应而形成。源极金属半导体合金与源极侧光晕区域的剩余部分相邻，从而将与源极区域连接的体接触部分连接到部分耗尽的SOI MOSFET。

23. 发明授权

US09379028B2 SOI CMOS structure having programmable floating backplate 有权
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US09379028B2
公开(公告)日：2016-06-28
申请号：US12619285
申请日：2009-11-16
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： H01L29/94 , H01L21/84 , H01L29/78 , H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

24. 发明授权

US09178061B2 Method for fabricating MOSFET on silicon-on-insulator with internal body contact 有权
标题翻译：用于在绝缘体上制造具有内部接触的绝缘体上的MOSFET的方法
公开(公告)号：US09178061B2
公开(公告)日：2015-11-03
申请号：US13572039
申请日：2012-08-10
申请人： Jin Cai , Steven J. Koester , Amlan Majumdar
发明人： Jin Cai , Steven J. Koester , Amlan Majumdar
IPC分类号： H01L21/28 , H01L21/44 , H01L29/78 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/41733 , H01L29/66659 , H01L29/7835 , H01L29/78612 , H01L29/78621
摘要： A method is provided for fabricating a semiconductor device. According to the method, a semiconductor layer is formed over a semiconductor-on-insulator substrate, and a gate is formed on the semiconductor layer. Source and drain extension regions and a deep drain region are formed in the semiconductor layer. A deep source region is formed in the semiconductor layer. A drain metal-semiconductor alloy contact is located on the upper portion of the deep drain region and abutting the drain extension region. A source metal-semiconductor alloy contact abuts the source extension region. The deep source region is located below and contacts a first portion of the source metal-semiconductor alloy contact. The deep source region is not located below and does not contact a second portion of the source metal-semiconductor alloy contact. The second portion of the source metal-semiconductor alloy contact is an internal body contact that directly contacts the semiconductor layer.
摘要翻译：提供了制造半导体器件的方法。根据该方法，在绝缘体上半导体基板上形成半导体层，在半导体层上形成栅极。源极和漏极延伸区域和深的漏极区域形成在半导体层中。在半导体层中形成深源区。漏极金属 - 半导体合金触点位于深漏区域的上部并邻接漏极延伸区域。源极金属 - 半导体合金接触件邻接源极延伸区域。深源区域位于源极金属 - 半导体合金接触件的第一部分下方并接触。深源区不位于源极金属 - 半导体合金触点的第二部分下方并且不接触。源极金属 - 半导体合金触点的第二部分是直接接触半导体层的内部主体接触。

25. 发明授权

US08946040B2 SOI lateral bipolar transistor having multi-sided base contact and methods for making same 有权
标题翻译：具有多边基极接触的SOI横向双极晶体管及其制造方法
公开(公告)号：US08946040B2
公开(公告)日：2015-02-03
申请号：US13343688
申请日：2012-01-04
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/10
CPC分类号： H01L27/082 , H01L21/8249 , H01L29/1004 , H01L29/42304 , H01L29/45 , H01L29/6625 , H01L29/735
摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.
摘要翻译：一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

26. 发明授权

US08705280B2 Electrically programmable floating common gate CMOS device and applications thereof 有权
标题翻译：电可编程浮动共栅CMOS器件及其应用
公开(公告)号：US08705280B2
公开(公告)日：2014-04-22
申请号：US12786956
申请日：2010-05-25
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , G11C16/0441 , H01L29/66825 , H01L29/7881
摘要： A programmable CMOS device includes a PFET and an NFET that have a common floating gate. Depending on the configuration, the programmable CMOS device can be programmed, erased, and re-programmed repeatedly. The programming, erasure, and/or reprogramming can be effected by injection of electrons and/or holes into the floating gate. The programmable CMOS device can be employed as a fuse or an antifuse, to program a floating gate of another device, and/or to function as a latch. The programmable CMOS device can be formed employing standard logic compatible processes, i.e., without employing any additional processing steps.
摘要翻译：可编程CMOS器件包括具有公共浮动栅极的PFET和NFET。根据配置，可重复编程，擦除和重新编程可编程CMOS器件。编程，擦除和/或重新编程可以通过将电子和/或空穴注入浮动栅极来实现。可编程CMOS器件可用作熔丝或反熔丝，以编程另一器件的浮置栅极和/或用作锁存器。可编程CMOS器件可以使用标准逻辑兼容工艺形成，即不需要任何额外的处理步骤。

27. 发明授权

US08557670B1 SOI lateral bipolar junction transistor having a wide band gap emitter contact 有权
标题翻译：具有宽带隙发射极接触的SOI横向双极结型晶体管
公开(公告)号：US08557670B1
公开(公告)日：2013-10-15
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

28. 发明申请

US20130256757A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 审中-公开
标题翻译：具有宽带带隙发射体接触的SOI侧向双极晶体管
公开(公告)号：US20130256757A1
公开(公告)日：2013-10-03
申请号：US13433537
申请日：2012-03-29
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

29. 发明申请

US20130200942A1 SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES 有权
公开(公告)号：US20130200942A1
公开(公告)日：2013-08-08
申请号：US13369261
申请日：2012-02-08
申请人： Jin Cai , Tak H. Ning
发明人： Jin Cai , Tak H. Ning
IPC分类号： G05F3/02
CPC分类号： H01L29/66234 , H01L21/761 , H01L27/082 , H01L27/1203 , H01L29/73
摘要： A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

30. 发明授权

US08441084B2 Horizontal polysilicon-germanium heterojunction bipolar transistor 有权
标题翻译：水平多晶硅 - 锗异质结双极晶体管
公开(公告)号：US08441084B2
公开(公告)日：2013-05-14
申请号：US13048342
申请日：2011-03-15
申请人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Kevin K. Chan , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L29/66 , H01L29/04
CPC分类号： H01L29/737 , H01L29/0808 , H01L29/0821 , H01L29/66242 , H01L29/66265
摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
摘要翻译：水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

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