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21. 发明申请

US20050124149A1 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer 有权
标题翻译：使用牺牲金属氧化物层形成双镶嵌金属互连的方法
公开(公告)号：US20050124149A1
公开(公告)日：2005-06-09
申请号：US10939930
申请日：2004-09-13
申请人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
发明人： Jae-Hak Kim , Young-Joon Moon , Kyoung-Woo Lee , Jeong-Wook Hwang
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76808 , H01L21/31144
摘要： There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.
摘要翻译：提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。该方法包括制备半导体衬底。在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

22. 发明授权

US06861347B2 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US06861347B2
公开(公告)日：2005-03-01
申请号：US10114274
申请日：2002-04-02
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76835
摘要： A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.
摘要翻译：提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。去除第一光致抗蚀剂图案。在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。同时去除第二光致抗蚀剂图案和有机材料层。通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

23. 发明授权

US09255204B2 Cavitation resistant polyurethane compositions and methods of forming coating films using the same 有权
标题翻译：防气蚀聚氨酯组合物和使用其制备涂膜的方法
公开(公告)号：US09255204B2
公开(公告)日：2016-02-09
申请号：US14204291
申请日：2014-03-11
申请人： Jun-Young Choi , Ja-Min Gu , Jae-Hak Kim
发明人： Jun-Young Choi , Ja-Min Gu , Jae-Hak Kim
IPC分类号： C08G18/22 , C08G18/40 , C08G18/44 , C08G18/48 , C08G18/72 , C08G18/76 , C08G18/79 , C08K3/04 , C09D5/00 , C09D7/12 , C09D175/04 , B82Y30/00 , B05D1/02 , C08G18/10 , C08L75/06 , C08L75/08 , C08G18/42 , C08L75/04
CPC分类号： C09D5/00 , B05D1/02 , B05D2202/00 , B82Y30/00 , C08G18/10 , C08G18/227 , C08G18/40 , C08G18/4018 , C08G18/4236 , C08G18/4277 , C08G18/44 , C08G18/48 , C08G18/4825 , C08G18/725 , C08G18/7671 , C08G18/797 , C08K3/04 , C08K3/22 , C08K3/34 , C08K3/38 , C08K5/36 , C08K5/43 , C08L75/06 , C08L75/08 , C09D7/67 , C09D175/04 , C08G18/42 , C08G18/12 , C08L75/04
摘要： A cavitation resistant polyurethane composition includes a first solution comprising a urethane prepolymer and a second solution. The urethane prepolymer is synthesized by a polymerization of about 60 to about 70 weight percent of an isocynate compound and about 30 to about 40 weight percent of a polyol. An average functional group number of the isocyanate compound is at least 2. The second solution includes about 90 to about 95 weight percent of a polyol having an average functional group number of at least 4, about 1 to about 3 weight percent of a nano-carbon, about 1 to about 3 weight percent of a colorant, about 1 to about 3 weight percent of a moisture absorbent, about 1 to about 3 weight percent of an anti-wear agent, and about 1 to about 3 weight percent of a defoaming agent.
摘要翻译：抗气蚀性聚氨酯组合物包括包含氨基甲酸酯预聚物和第二溶液的第一溶液。氨基甲酸酯预聚物通过约60至约70重量％的异氰酸酯化合物和约30至约40重量％的多元醇的聚合合成。异氰酸酯化合物的平均官能团数为至少2.第二溶液包含约90-约95重量％的平均官能团数为至少4，约1至约3重量％的纳米 - 碳，约1至约3重量％的着色剂，约1至约3重量％的吸湿剂，约1至约3重量％的抗磨剂和约1至约3重量％的消泡剂代理商

24. 发明申请

US20130224371A1 Method of Manufacturing Electrodes using Carbon nanotube Sheets 有权
标题翻译：使用碳纳米管片制造电极的方法
公开(公告)号：US20130224371A1
公开(公告)日：2013-08-29
申请号：US13854747
申请日：2013-04-01
申请人： Jae Hak Kim , Gil Sik Lee , Kyung Hwan Lee , Lawrence J. Overzet
发明人： Jae Hak Kim , Gil Sik Lee , Kyung Hwan Lee , Lawrence J. Overzet
IPC分类号： H01M4/04 , H01M4/88
CPC分类号： H01M4/0402 , B82Y30/00 , B82Y40/00 , C01B32/15 , D01F9/127 , D01F9/1275 , H01M4/88 , Y10S977/742
摘要： Growing spin-capable multi-walled carbon nanotube (MWCNT) forests in a repeatable fashion will become possible through understanding the critical factors affecting the forest growth. Here we show that the spinning capability depends on the alignment of adjacent MWCNTs in the forest which in turn results from the synergistic combination of a high areal density of MWCNTs and short distance between the MWCNTs. This can be realized by starting with both the proper Fe nanoparticle size and density which strongly depend on the sheet resistance of the catalyst film. Simple measurement of the sheet resistance can allow one to reliably predict the growth of spin-capable forests. The properties of pulled MWCNTs sheets reflect that there is a relationship between their electrical resistance and optical transmittance. Overlaying either 3, 5, or 10 sheets pulled out from a single forest produces much more repeatable characteristics.
摘要翻译：通过了解影响森林生长的关键因素，可以以可重复的方式种植自旋多壁碳纳米管（MWCNT）。这里我们表明，纺丝能力取决于森林中相邻的MWCNT的排列，这反过来又是MWCNT的高密度密度与MWCNT之间的短距离的协同组合。这可以通过从适当的Fe纳米颗粒尺寸和密度开始，这强烈地取决于催化剂膜的薄层电阻。简单测量薄层电阻可以使人们能够可靠地预测可旋转森林的生长。拉伸的MWCNT片材的性质反映了它们的电阻和光透射率之间存在关系。从单个森林中抽出的3张，5张或10张纸叠加出更多的可重复特征。

25. 发明授权

US08409768B2 Tuning of Fe catalysts for growth of spin-capable carbon nanotubes 失效
标题翻译：用于自旋能碳纳米管生长的Fe催化剂的调谐
公开(公告)号：US08409768B2
公开(公告)日：2013-04-02
申请号：US12902392
申请日：2010-10-12
申请人： Jae Hak Kim , Gil Sik Lee , Kyung Hwan Lee , Lawrence J. Overzet
发明人： Jae Hak Kim , Gil Sik Lee , Kyung Hwan Lee , Lawrence J. Overzet
IPC分类号： B82Y30/00 , B82Y40/00 , C01B31/02 , D01F9/127
CPC分类号： H01M4/0402 , B82Y30/00 , B82Y40/00 , C01B32/15 , D01F9/127 , D01F9/1275 , H01M4/88 , Y10S977/742
摘要： Growing spin-capable multi-walled carbon nanotube (MWCNT) forests in a repeatable fashion will become possible through understanding the critical factors affecting the forest growth. Here we show that the spinning capability depends on the alignment of adjacent MWCNTs in the forest which in turn results from the synergistic combination of a high areal density of MWCNTs and short distance between the MWCNTs. This can be realized by starting with both the proper Fe nanoparticle size and density which strongly depend on the sheet resistance of the catalyst film. Simple measurement of the sheet resistance can allow one to reliably predict the growth of spin-capable forests. The properties of pulled MWCNTs sheets reflect that there is a relationship between their electrical resistance and optical transmittance. Overlaying either 3, 5, or 10 sheets pulled out from a single forest produces much more repeatable characteristics.
摘要翻译：通过了解影响森林生长的关键因素，可以以可重复的方式种植自旋多壁碳纳米管（MWCNT）。这里我们表明，纺丝能力取决于森林中相邻的MWCNT的排列，这反过来又是MWCNT的高密度密度与MWCNT之间的短距离的协同组合。这可以通过从适当的Fe纳米颗粒尺寸和密度开始，这强烈地取决于催化剂膜的薄层电阻。简单测量薄层电阻可以使人们能够可靠地预测可旋转森林的生长。拉伸的MWCNT片材的性质反映了它们的电阻和光透射率之间存在关系。从单个森林中抽出的3张，5张或10张纸叠加出更多的可重复特征。

26. 发明申请

US20100170631A1 FOLDING AND SHAPE-FORMING APPARATUS AND METHOD FOR PREPREG 有权
标题翻译：折叠和成型设备和PREPREG方法
公开(公告)号：US20100170631A1
公开(公告)日：2010-07-08
申请号：US12411309
申请日：2009-03-25
申请人： Jae Hak KIM , Joong Won Han , Jae Hwan Lee , Do Young Lee , Jin Hyun Kim
发明人： Jae Hak KIM , Joong Won Han , Jae Hwan Lee , Do Young Lee , Jin Hyun Kim
IPC分类号： B29C51/10 , B29C63/16
CPC分类号： B29C70/44 , B29C53/025 , B29C2791/006 , B29L2031/003 , Y10T156/1028
摘要： Disclosed is a folding and shape-forming apparatus for a prepreg which includes a vacuum chamber which can generate a vacuum pressure in the inside thereof, an expanding portion disposed inside the vacuum chamber, provided with a prepreg thereon, and expanding because of the vacuum pressure inside the vacuum chamber, a heating portion disposed inside the vacuum chamber for heating the prepreg, a mandrel loaded at a portion of an upper surface of the prepreg, a first pressing portion which is brought into contact with an upper surface of the mandrel to press the mandrel, and a second pressing portion which simultaneously presses both another portion of the upper surface of the prepreg and the expanding portion.
摘要翻译：公开了一种用于预浸料的折叠和成形装置，其包括可在其内部产生真空压力的真空室，设置在真空室内的膨胀部分，在其上设置有预浸料，并且由于真空压力而膨胀在真空室内部，设置在真空室内用于加热预浸料的加热部分，装在预浸料坯上表面部分的芯棒，与心轴上表面接触的第一按压部分心轴以及同时按压预浸料坯的上表面的另一部分和膨胀部的第二挤压部。

27. 发明授权

US07635645B2 Method for forming interconnection line in semiconductor device and interconnection line structure 有权
标题翻译：在半导体器件和互连线结构中形成互连线的方法
公开(公告)号：US07635645B2
公开(公告)日：2009-12-22
申请号：US11028515
申请日：2005-01-04
申请人： Kyoung-Woo Lee , Hong-Jae Shin , Jae-Hak Kim , Young-Jin Wee , Seung-Jin Lee , Ki-Kwan Park
发明人： Kyoung-Woo Lee , Hong-Jae Shin , Jae-Hak Kim , Young-Jin Wee , Seung-Jin Lee , Ki-Kwan Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76814 , H01L21/76829
摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.
摘要翻译：公开了形成互连线和互连线结构的方法。该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。在层间绝缘层上形成氧化阻隔层。在氧化阻挡层上形成氧化物覆盖层。通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。导电层图案形成在通孔内。

28. 发明申请

US20090280637A1 Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
标题翻译：包括超低介电常数层的半导体器件的制造方法
公开(公告)号：US20090280637A1
公开(公告)日：2009-11-12
申请号：US12453326
申请日：2009-05-07
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层半导体器件。该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔，形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

29. 发明申请

US20090239374A1 Methods of Forming Metal Interconnect Structures on Semiconductor Substrates Using Oxygen-Removing Plasmas and Interconnect Structures Formed Thereby 有权
标题翻译：使用除氧等离子体和互连结构形成半导体基板上的金属互连结构的方法
公开(公告)号：US20090239374A1
公开(公告)日：2009-09-24
申请号：US12050354
申请日：2008-03-18
申请人： Jae hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
发明人： Jae hak Kim , Griselda Bonilla , Steven E. Molis , Darryl D. Restaino , Hosadurga Shobha , Johnny Widodo
IPC分类号： H01L21/4763
CPC分类号： H01L23/53233 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76876 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.
摘要翻译：形成器件的方法包括在衬底上形成其中具有金属互连的第一电绝缘层，然后在金属互连的上表面上和第一电绝缘层上形成第一电绝缘阻挡层。第一电绝缘阻挡层暴露于穿过第一电绝缘屏障并从金属互连的上表面除去氧的等离子体。阻挡层的厚度可以在约5至约埃的范围内，等离子体可以是将金属互连的上表面上的氧转化为水的含氢等离子体。

30. 发明授权

US07488687B2 Methods of forming electrical interconnect structures using polymer residues to increase etching selectivity through dielectric layers 有权
标题翻译：使用聚合物残余物形成电互连结构以通过介电层增加蚀刻选择性的方法
公开(公告)号：US07488687B2
公开(公告)日：2009-02-10
申请号：US11530952
申请日：2006-09-12
申请人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
发明人： Wan Jae Park , Jae Hak Kim , Tong Qing Chen , Yi-hsiung Lin
IPC分类号： H01L21/00
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31116 , H01L21/31144
摘要： Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.
摘要翻译：形成电互连结构的方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。在硬掩模层的上表面上形成光刻胶层。该图案化的光致抗蚀剂层在步骤期间用作蚀刻掩模，以选择性地蚀刻硬掩模层并在其中限定开口。该开口露出第一电介质层。然后使用暴露硬掩模层的上表面的灰化处理从硬掩模层剥离图案化的光致抗蚀剂层。在该灰化处理之后，使用硬掩模层作为蚀刻掩模来选择性地蚀刻与开口相对延伸的第一电介质层的一部分。在该选择蚀刻步骤期间，聚合物残留物直接堆积在硬掩模层的上表面上。在选择性蚀刻第一介电层的步骤期间，这些聚合物残余物可以操作以增加选择性的程度并抑制硬掩模层的凹陷。

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