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21. 发明申请

US20090017577A1 Methods of Forming Phase Change Memory Devices Having Bottom Electrodes 有权
标题翻译：形成具有底部电极的相变存储器件的方法
公开(公告)号：US20090017577A1
公开(公告)日：2009-01-15
申请号：US12170038
申请日：2008-07-09
申请人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
发明人： Hyeong-Geun An , Dong-Ho Ahn , Young-Soo Lim , Yong-Ho Ha , Jun-Young Jang , Dong-Won Lim , Gyeo-Re Lee , Joon-Sang Park , Han-Bong Ko , Young-Lim Park
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/16 , Y10S438/90
摘要： Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction.
摘要翻译：相变存储器件可以在衬底上具有底部图案。线形或L形底部电极可以形成为与衬底上的相应底部图案接触并且具有由衬底上沿x和y轴方向的尺寸限定的顶表面。沿着底部电极的顶表面的x轴的尺寸比用于制造相变存储器件的光刻工艺的分辨率极限具有更小的宽度。相变图案可以形成为与底部电极的顶表面接触以具有比底部电极的顶表面的x和y轴方向上的每个尺寸更大的宽度，并且顶部电极可以形成在相位上其中线形或L形表示底部电极在x轴方向上的截面线形状或截面L形。

22. 发明申请

US20080237566A1 Phase change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20080237566A1
公开(公告)日：2008-10-02
申请号：US11905244
申请日：2007-09-28
申请人： Hyeong-Geun AN , Hideki HORII , Jong-Chan SHIN , Dong-Ho AHN , Jun-Soo BAE , Jeong-Hee PARK
发明人： Hyeong-Geun AN , Hideki HORII , Jong-Chan SHIN , Dong-Ho AHN , Jun-Soo BAE , Jeong-Hee PARK
IPC分类号： H01L47/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1683
摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane
摘要翻译：提供了一种相变存储器件及其制造方法。具有第一表面的第一电极设置在基板上。具有与第一表面不同的第二表面的第二电极在基板上。第二电极可以与第一电极间隔开。可以对应于第一电极形成第三电极。可以对应于第二电极形成第四电极。可以在第一表面和第三电极之间插入第一相变图案。可以在第二表面和第四电极之间插入第二相变图案。第一和第二相变图案的上表面可以在同一平面上

23. 发明申请

US20080149910A1 PHASE-CHANGE MEMORY DEVICE HAVING PHASE CHANGE MATERIAL PATTERN SHARED BETWEEN ADJACENT CELLS AND ELECTRONIC PRODUCT INCLUDING THE PHASE-CHANGE MEMORY 有权
标题翻译：具有相变细胞之间的相变材料相位变化的相变存储器件和包括相变存储器的电子产品
公开(公告)号：US20080149910A1
公开(公告)日：2008-06-26
申请号：US11941173
申请日：2007-11-16
申请人： Hyeong-geun AN , Hideki HORII , Jong-chan SHIN , Dong-ho AHN , Jun-soo BAE
发明人： Hyeong-geun AN , Hideki HORII , Jong-chan SHIN , Dong-ho AHN , Jun-soo BAE
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.
摘要翻译：提供了一种相变存储器件，其包括相邻单元共享条带的相变材料图案。相变存储器件包括以矩阵阵列排列的多个底部电极。相变材料图案形成在底部电极上，相变材料图案的条带电连接到底部电极。相变材料图案的每个条带连接到底部电极的至少两个对角相邻的底部电极。

24. 发明申请

US20080070344A1 PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same 有权
标题翻译： PRAMS具有顺序地定位的多个活性区域和形成该活性区域的方法
公开(公告)号：US20080070344A1
公开(公告)日：2008-03-20
申请号：US11982940
申请日：2007-11-06
申请人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
发明人： Jae-Hyun Park , Hyeong-Geun An , Su-Jin Ahn , Yoon-Jong Song , Hyung-Joo Youn , Kyu-Chul Kim
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/144
摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
摘要翻译：提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。其他半导体衬底分别限定其它有源区。在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

25. 发明授权

US07064365B2 Ferroelectric capacitors including a seed conductive film 失效
标题翻译：铁电电容器包括种子导电膜
公开(公告)号：US07064365B2
公开(公告)日：2006-06-20
申请号：US10705680
申请日：2003-11-10
申请人： Hyeong-Geun An , Sang-Woo Lee , Hyoung-Joon Kim
发明人： Hyeong-Geun An , Sang-Woo Lee , Hyoung-Joon Kim
IPC分类号： H01L29/76
CPC分类号： H01L28/75 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.
摘要翻译：铁电电容器包括集成电路基板上的支撑绝缘膜并且在其中具有沟槽。下电极位于沟槽的侧壁和底表面上。种子导电膜覆盖下电极。在支撑绝缘膜和种子导电膜上设置铁电体膜，在铁电体膜上设置上电极。下电极可以填充沟槽，并且铁电膜可以延伸到与种子导电膜相邻的种子导电膜和支撑绝缘膜上。

26. 发明授权

US07023037B2 Integrated circuit devices having dielectric regions protected with multi-layer insulation structures 有权
标题翻译：具有由多层绝缘结构保护的电介质区域的集成电路器件
公开(公告)号：US07023037B2
公开(公告)日：2006-04-04
申请号：US10813335
申请日：2004-03-30
申请人： Hag-ju Cho , Hyeong-geun An
发明人： Hag-ju Cho , Hyeong-geun An
IPC分类号： H01L29/76
CPC分类号： H01L27/11502 , H01L28/55
摘要： A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
摘要翻译：诸如集成电路电容器的铁电电介质区域的电介质区域由包括第一相对薄的绝缘层（例如，氧化铝或其它金属氧化物层）的多层绝缘结构和第二较厚绝缘层层，例如第二氧化铝或其它金属氧化物层。在形成第二绝缘层之前，第一绝缘层和电介质优选退火，这可以增加电介质区域的剩余极化。第一绝缘层可以在形成第二绝缘层和其它上覆结构期间用作氢扩散阻挡层。以这种方式，可以降低电介质的劣化。讨论了器件和制造方法。

27. 发明授权

US08625325B2 Memory cells including resistance variable material patterns of different compositions 有权
标题翻译：记忆单元包括不同组成的电阻变化材料图案
公开(公告)号：US08625325B2
公开(公告)日：2014-01-07
申请号：US12853329
申请日：2010-08-10
申请人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
发明人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
IPC分类号： G11C11/56
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2213/56 , G11C2213/72 , H01L27/101
摘要： A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
摘要翻译：非易失性存储器件包括多个字线，多个位线，以及每个电连接在相应字线和相应位线之间的可变电阻存储单元阵列。每个存储单元包括在第一和第二电极之间串联电连接的第一和第二电阻可变图案。第一电阻可变图案的材料组成不同于第二电阻变化图案的材料组成。每个存储器单元的多位数据状态由第一和第二电阻变化模式内的可编程高电阻体积的连续增加来定义。

28. 发明授权

US08039829B2 Contact structure, a semiconductor device employing the same, and methods of manufacturing the same 有权
标题翻译：接触结构，采用该接触结构的半导体器件及其制造方法
公开(公告)号：US08039829B2
公开(公告)日：2011-10-18
申请号：US12412657
申请日：2009-03-27
申请人： Jeong-Hee Park , Yong-Ho Ha , Hyeong-Geun An , Joon-Sang Park , Hyun-Suk Kwon , Myung-Jin Kang , Doo-Hwan Park
发明人： Jeong-Hee Park , Yong-Ho Ha , Hyeong-Geun An , Joon-Sang Park , Hyun-Suk Kwon , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1666
摘要： A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern.
摘要翻译：一种接触结构，其包括形成在基板上的第一图案，其中所述第一图案在其上表面具有凹陷区域，形成在所述第一图案上的平坦化缓冲图案，以及形成在所述平坦化缓冲图案上的导电图案。

29. 发明申请

US20110032753A1 MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS 有权
标题翻译：包含不同成分的电阻变化材料的记忆细胞
公开(公告)号：US20110032753A1
公开(公告)日：2011-02-10
申请号：US12853329
申请日：2010-08-10
申请人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
发明人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2213/56 , G11C2213/72 , H01L27/101
摘要： A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
摘要翻译：非易失性存储器件包括多个字线，多个位线，以及每个电连接在相应字线和相应位线之间的可变电阻存储单元阵列。每个存储单元包括在第一和第二电极之间串联电连接的第一和第二电阻可变图案。第一电阻可变图案的材料组成不同于第二电阻变化图案的材料组成。每个存储器单元的多位数据状态由第一和第二电阻变化模式内的可编程高电阻体积的连续增加来定义。

30. 发明申请

US20110032752A1 Multi-Level Memory Device Using Resistance Material 有权
标题翻译：使用电阻材料的多级存储器件
公开(公告)号：US20110032752A1
公开(公告)日：2011-02-10
申请号：US12819498
申请日：2010-06-21
申请人： Ik-Soo Kim , Do-Hyung KIM , Sung-Lae CHO , Hyeong-Geun AN , Dong-Hyun IM , Eun-Hee CHO
发明人： Ik-Soo Kim , Do-Hyung KIM , Sung-Lae CHO , Hyeong-Geun AN , Dong-Hyun IM , Eun-Hee CHO
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5685 , G11C8/08 , G11C11/5678 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： A multi-level memory device includes an insulating layer having an opening therein, and a multi-level cell (MLC) formed in the opening that has a resistance level varies based on the data stored therein. The MLC is configured to have a resistance level that varies as write pulses having the same pulse height and different pulse widths are applied to the MLC.
摘要翻译：多级存储器件包括其中具有开口的绝缘层，并且形成在开口中的具有电阻电平的多电平单元（MLC）基于存储在其中的数据而变化。 MLC被配置为具有随着具有相同脉冲高度和不同脉冲宽度的写入脉冲被施加到MLC而变化的电阻电平。

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