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21. 发明授权

US07008866B2 Large-scale trimming for ultra-narrow gates 有权
标题翻译：超窄门的大规模修剪
公开(公告)号：US07008866B2
公开(公告)日：2006-03-07
申请号：US10738239
申请日：2003-12-17
申请人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
发明人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/28123
摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.
摘要翻译：公开了用于形成用于半导体器件的超窄栅极的大规模修整。蚀刻在半导体晶片上的图案化软掩模层下方的半导体晶片上的硬掩模层，以使硬掩模层的宽度变窄。修剪硬掩模层以进一步缩小已经去除软掩模层的硬掩模层的宽度。蚀刻半导体晶片上的硬掩模层下方的至少栅极电极层，导致栅极电极层的宽度与被修整的硬掩模层的宽度基本相同。蚀刻的栅极电极层形成半导体晶片上的超窄栅电极，其中硬掩模层被去除。

22. 发明申请

US20050184388A1 Seal ring design without stop layer punch through during via etch 审中-公开
标题翻译：密封圈设计，无停止层通孔蚀刻过程中
公开(公告)号：US20050184388A1
公开(公告)日：2005-08-25
申请号：US10782365
申请日：2004-02-19
申请人： Hsin-Ching Shih , Kang-Cheng Lin , Chao-Cheng Chen , Hun-Jan Tao
发明人： Hsin-Ching Shih , Kang-Cheng Lin , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L23/48 , H01L23/58
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.
摘要翻译：根据本发明的目的，提供了一种用于创建具有不同元件的密封环的新方法。密封环的临界尺寸相对于其它装置特征（例如密封通孔）的CD被选择，使得所产生的密封环和通孔之间的蚀刻敏感性的差异被去除。同时蚀刻的特征的所有蚀刻同时完成，避免冲蚀下一层蚀刻停止材料。

23. 发明申请

US20050181590A1 Process for patterning high-k dielectric material 有权
标题翻译：图案化高k电介质材料的工艺
公开(公告)号：US20050181590A1
公开(公告)日：2005-08-18
申请号：US11101774
申请日：2005-04-08
申请人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Baw-Ching Perng , Hun-Jan Tao
IPC分类号： C23F1/00 , H01L21/20 , H01L21/28 , H01L21/306 , H01L21/311 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L21/31144 , H01L21/31116
摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.
摘要翻译：提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。在高k电介质层上进行第一蚀刻。在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。第二蚀刻不同于第一蚀刻。优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

24. 发明申请

US20050179098A1 Method to form a metal silicide gate device 失效
标题翻译：形成金属硅化物栅极器件的方法
公开(公告)号：US20050179098A1
公开(公告)日：2005-08-18
申请号：US10780513
申请日：2004-02-17
申请人： Bor-Wen Chan , Chih-Hao Wang , Lawrance Hsu , Hun-Jan Tao
发明人： Bor-Wen Chan , Chih-Hao Wang , Lawrance Hsu , Hun-Jan Tao
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/28097 , H01L21/823425 , H01L21/823443 , H01L21/823462 , H01L21/823835 , H01L21/823857 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.
摘要翻译：实现了在制造集成电路器件中形成金属硅化物栅极的新方法。该方法包括在其间具有介电层的衬底上形成多晶硅线。第一隔离层形成在衬底和多晶硅线的侧壁上。第一隔离层不覆盖多晶硅线的顶表面。多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。金属层沉积在多晶硅线上。使用热退火将多晶硅线完全转换成金属硅化物栅极。去除未反应的金属层以完成该装置。

25. 发明申请

US20050133830A1 Method for fabricating a recessed channel filed effect transistor (FET) device 失效
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US20050133830A1
公开(公告)日：2005-06-23
申请号：US10739476
申请日：2003-12-17
申请人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L29/786 , H01L21/8234 , H01L29/76 , H01L31/113
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

26. 发明申请

US20050118755A1 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US20050118755A1
公开(公告)日：2005-06-02
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Fang-Chen Cheng , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L29/40
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

27. 发明申请

US20050106888A1 Method of in-situ damage removal - post O2 dry process 审中-公开
标题翻译：原位损伤去除方法 - 后O2干法
公开(公告)号：US20050106888A1
公开(公告)日：2005-05-19
申请号：US10714207
申请日：2003-11-14
申请人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Ching Chang , Hun-Jan Tao
IPC分类号： G03F7/42 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/461 , H01L21/768
CPC分类号： H01L21/31116 , G03F7/427 , H01L21/02046 , H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814
摘要： An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.
摘要翻译：公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是可以单独使用或与上述含卤素气体中的一种一起使用。氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

28. 发明授权

US06867084B1 Gate structure and method of forming the gate dielectric with mini-spacer 有权
标题翻译：用微型间隔物形成栅极电介质的栅结构和方法
公开(公告)号：US06867084B1
公开(公告)日：2005-03-15
申请号：US10263541
申请日：2002-10-03
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Fang-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/265 , H01L21/8238 , H01L29/78 , H01L29/80
CPC分类号： H01L21/2652 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.
摘要翻译：描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。然后将高k电介质材料衬垫沉积在所有暴露的表面上。然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件硅衬底。

29. 发明授权

US06864193B2 Aqueous cleaning composition containing copper-specific corrosion inhibitor 失效
标题翻译：含有铜特异性缓蚀剂的水性清洗组合物
公开(公告)号：US06864193B2
公开(公告)日：2005-03-08
申请号：US10379769
申请日：2003-03-05
申请人： Chun-Li Chou , Hun-Jan Tao , Peng-Fu Hsu
发明人： Chun-Li Chou , Hun-Jan Tao , Peng-Fu Hsu
IPC分类号： C11D7/26 , C11D7/50 , C11D11/00 , H01L21/00 , H01L21/02 , H01L21/306 , H01L21/311 , H01L21/321 , H01L21/461
CPC分类号： H01L21/02063 , C11D7/261 , C11D7/263 , C11D7/265 , C11D7/267 , C11D7/5022 , C11D11/0047 , Y10S438/905 , Y10S438/906
摘要： A composition and method for fabricating a semiconductor wafer containing copper is disclosed, which method includes plasma etching a dielectric layer from the surface of the wafer, plasma ashing a resist from the surface of the wafer, and cleaning the wafer surface by contacting same with a cleaning formulation, which includes the following components and their percentage by weight ranges shown: (a) from about 0.01 to 80% by weight organic solvent, (b) from about 0.01 to 30% by weight copper chelating agent, (c) from about 0.01 to 10% by weight copper inhibitor, and (d) from about 0.01 to 70% by weight water.
摘要翻译：公开了一种用于制造含有铜的半导体晶片的组合物和方法，该方法包括从晶片的表面等离子体蚀刻介电层，等离子体从晶片的表面灰化抗蚀剂，以及通过使晶片表面与清洁制剂，其包括以下组分及其重量百分比范围：（a）约0.01至80重量％的有机溶剂，（b）约0.01至30重量％的铜螯合剂，（c）约 0.01〜10重量％的铜抑制剂，（d）约0.01〜70重量％的水。

30. 发明授权

US06828248B1 Method of pull back for forming shallow trench isolation 失效
标题翻译：用于形成浅沟槽隔离的拉回方法
公开(公告)号：US06828248B1
公开(公告)日：2004-12-07
申请号：US10637350
申请日：2003-08-08
申请人： Hun-Jan Tao , Huan-Just Lin
发明人： Hun-Jan Tao , Huan-Just Lin
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/3081 , H01L21/3086 , H01L21/76232
摘要： A method of pull back for a shallow trench isolation (STI) structure is provided. The method firstly provides a substrate having a hard mask layer disposed thereupon and a dielectric layer above the hard mask layer. Then a trench is formed within the hard mask layer, the dielectric layer and the substrate. Finally, the hard mask layer and the dielectric layer are pulled back by using a halogen containing etching process.
摘要翻译：提供了一种用于浅沟槽隔离（STI）结构的拉回方法。该方法首先提供具有设置在其上的硬掩模层和硬掩模层上方的电介质层的衬底。然后在硬掩模层，电介质层和衬底内形成沟槽。最后，通过使用含卤素蚀刻工艺将硬掩模层和电介质层拉回。

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