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21. 发明申请

US20070216042A1 Methods for manufacturing compound-material wafers and for recycling used donor substrates 有权
标题翻译：用于制造复合材料晶片和用于再循环使用的供体基板的方法
公开(公告)号：US20070216042A1
公开(公告)日：2007-09-20
申请号：US11472693
申请日：2006-06-21
申请人： Daniel Delprat , Eric Neyret , Oleg Kononchuk , Patrick Reynaud , Michael Stinco
发明人： Daniel Delprat , Eric Neyret , Oleg Kononchuk , Patrick Reynaud , Michael Stinco
IPC分类号： H01L21/322
CPC分类号： H01L21/02032 , H01L21/76254
摘要： This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.
摘要翻译：本发明提供了用于制造复合材料晶片的方法以及由制造复合材料晶片产生的用于再循环施主衬底的方法。所提供的方法包括至少一个另外的热处理步骤，其被配置为至少部分地减少氧沉淀物和/或核。减少氧沉淀物和/或核，提高了供体底物的再循环率。

22. 发明申请

US20070148910A1 Process for simplification of a finishing sequence and structure obtained thereby 有权
标题翻译：简化由此得到的精整序列和结构的方法
公开(公告)号：US20070148910A1
公开(公告)日：2007-06-28
申请号：US11356926
申请日：2006-02-16
申请人： Eric Neyret , Alice Boussagol , Nadia Ben Mohamed
发明人： Eric Neyret , Alice Boussagol , Nadia Ben Mohamed
IPC分类号： H01L21/46 , H01L29/02
CPC分类号： H01L21/76254
摘要： The invention relates to a process for the formation of a structure comprising a thin layer made of semiconductor material on a substrate, including the steps of providing a zone of weakness in a donor substrate; bonding the donor substrate to a support substrate; detaching a portion of the donor substrate to transfer it to the support substrate, wherein the detaching includes applying heat treating the donor substrate to weaken the zone of weakness without initiating detachment and applying an energy pulse to provoke self-maintained detachment of the donor substrate portion to transfer it to the support substrate; and subjecting the transferred portion of the donor substrate to a finishing operation to form a thin layer. The finishing operation is simplified compared to that which is conducted by a conventional process that achieves detaching by applying a heat treatment to provoke self-maintained detachment of the donor substrate portion, and the thin layer has a surface of the same smoothness as one prepared by the conventional process.
摘要翻译：本发明涉及一种用于形成包括由衬底上的半导体材料制成的薄层的结构的方法，包括以下步骤：在施主衬底中提供弱化区; 将施主衬底粘合到支撑衬底上; 分离供体基质的一部分以将其转移到支撑基底，其中分离包括施加热处理供体基底以弱化弱化区而不引发脱离并施加能量脉冲以引发供体基底部分的自维持脱离将其转移到支撑基板上; 并且对被转移的供体基底进行精加工操作以形成薄层。与通过施加热处理以实现供体基板部分的自我维持的分离而实现分离的常规方法进行的精加工操作相比，该薄层具有与由常规方法。

23. 发明申请

US20060024908A1 Method of reducing the surface roughness of a semiconductor wafer 有权
标题翻译：降低半导体晶片的表面粗糙度的方法
公开(公告)号：US20060024908A1
公开(公告)日：2006-02-02
申请号：US11189899
申请日：2005-07-27
申请人： Eric Neyret , Ludovic Ecarnot , Emmanuel Arene
发明人： Eric Neyret , Ludovic Ecarnot , Emmanuel Arene
IPC分类号： H01L21/20
CPC分类号： H01L21/3247 , H01L21/302 , H01L21/324 , H01L21/76254
摘要： A method for reducing the roughness of a free surface of a semiconductor wafer that includes establishing a first atmosphere in an annealing chamber, replacing the first atmosphere with a second atmosphere that includes a gas selected to and in an amount to substantially eliminate or reduce pollutants on a wafer, and exposing the free surface of the wafer to the second atmosphere to substantially eliminate or reduce pollutants thereon. The second atmosphere is then replaced with a third atmosphere that includes pure, and rapid thermal annealing is performed on the wafer exposed to the third atmosphere in the annealing chamber to substantially reduce the roughness of the free surface of the wafer.
摘要翻译：一种用于降低半导体晶片的自由表面的粗糙度的方法，其包括在退火室中建立第一气氛，用第二气氛代替第一气氛，所述第二气氛包括选择的量和基本上消除或减少污染物的量晶片，并且将晶片的自由表面暴露于第二气氛以基本上消除或减少其上的污染物。然后将第二气氛替换为包括纯的第三气氛，并且在退火室中暴露于第三气氛的晶片上进行快速热退火，以显着降低晶片的自由表面的粗糙度。

24. 发明申请

US20050094990A1 Heat treatment for edges of multilayer semiconductor wafers 有权
标题翻译：多层半导体晶片边缘的热处理
公开(公告)号：US20050094990A1
公开(公告)日：2005-05-05
申请号：US11008928
申请日：2004-12-13
申请人： Eric Neyret , Christophe Maleville
发明人： Eric Neyret , Christophe Maleville
IPC分类号： H01L21/00 , H01L21/324 , H01L21/762 , H01L21/3205 , A21B2/00 , F26B19/00 , H01L21/26 , H01L21/42 , H01L21/4763 , H01L21/477
CPC分类号： H01L21/3247 , H01L21/67103 , H01L21/76251 , H01L21/76254
摘要： A method for heat treating a multilayer semiconductor wafer having a central region and a peripheral edge each having a surface. The method includes selecting thickness values for the layers of the wafer to provide substantially equivalent heat absorption coefficients both in the central region and the edge of the wafer. This results in a substantially equivalent temperature being attained over the surface of the central region and the peripheral edge during thermal treatment. In turn, that prevents the appearance of slip lines on those surfaces while also preventing deformation of the wafer due to the thermal treatment. To achieve the desired thickness, layers or portions of layers can be selectively added or otherwise provided upon the central region or peripheral edge of the wafer, or on both, to modify the heat absorption coefficient of the wafer.
摘要翻译：一种用于热处理具有各自具有表面的中心区域和周缘的多层半导体晶片的方法。该方法包括选择晶片层的厚度值，以在晶片的中心区域和边缘提供基本相等的吸热系数。这导致在热处理期间在中心区域和外围边缘的表面上获得基本相当的温度。反过来，这也防止了在这些表面上的滑动线的出现，同时也防止了由于热处理导致的晶片的变形。为了实现所需的厚度，层或层的一部分可以选择性地添加或以其他方式设置在晶片的中心区域或周边边缘上，或者在两者上，以改变晶片的吸热系数。

25. 发明授权

US08389412B2 Finishing method for a silicon on insulator substrate 有权
标题翻译：硅绝缘体衬底的整理方法
公开(公告)号：US08389412B2
公开(公告)日：2013-03-05
申请号：US13257164
申请日：2010-03-17
申请人： Walter Schwarzenbach , Sébastien Kerdiles , Patrick Reynaud , Ludovic Ecarnot , Eric Neyret
发明人： Walter Schwarzenbach , Sébastien Kerdiles , Patrick Reynaud , Ludovic Ecarnot , Eric Neyret
IPC分类号： H01L21/311
CPC分类号： H01L21/76254 , H01L21/02238 , H01L21/02255 , H01L21/02312 , H01L21/30604 , H01L21/31662
摘要： The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.
摘要翻译：本发明涉及一种绝缘体上硅（SOI）衬底的精加工方法，其包括埋在有源硅层和硅支承层之间的氧化物层。该方法包括以下步骤：SOI衬底的第一快速热退火（RTA）; 用于去除第一氧化物厚度的衬底的有源硅层的牺牲氧化; 底物的第二RTA; 并且对所述有源硅层进行第二牺牲氧化，以去除比所述第一氧化物厚度更薄的第二氧化物厚度。

26. 发明申请

US20110097874A1 PROGRESSIVE TRIMMING METHOD 有权
标题翻译：循序渐进的方法
公开(公告)号：US20110097874A1
公开(公告)日：2011-04-28
申请号：US12934026
申请日：2009-07-31
申请人： Marcel Broekaart , Marion Migette , Sebastian Molinari , Eric Neyret
发明人： Marcel Broekaart , Marion Migette , Sebastian Molinari , Eric Neyret
IPC分类号： H01L21/304 , H01L21/306 , B24B1/00
CPC分类号： H01L21/304 , H01L21/76256 , H01L25/50 , H01L2225/06513 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.
摘要翻译：本发明提供了一种修整结构的方法，该结构包括与第二晶片结合的第一晶片，其中第一晶片具有倒角边缘。该方法包括在第一深度上执行的第一修整步骤，该第一深度至少包括第一晶片的厚度以及从第一晶片的边缘确定的第一宽度。然后在包括至少第一晶片的厚度和小于第一宽度的第二宽度的第二深度上进行第二修整步骤。

27. 发明授权

US07883628B2 Method of reducing the surface roughness of a semiconductor wafer 有权
标题翻译：降低半导体晶片的表面粗糙度的方法
公开(公告)号：US07883628B2
公开(公告)日：2011-02-08
申请号：US11189899
申请日：2005-07-27
申请人： Eric Neyret , Ludovic Ecarnot , Emmanuel Arene
发明人： Eric Neyret , Ludovic Ecarnot , Emmanuel Arene
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/3247 , H01L21/302 , H01L21/324 , H01L21/76254
摘要： A method for reducing the roughness of a free surface of a semiconductor wafer that includes establishing a first atmosphere in an annealing chamber, replacing the first atmosphere with a second atmosphere that includes a gas selected to and in an amount to substantially eliminate or reduce pollutants on a wafer, and exposing the free surface of the wafer to the second atmosphere to substantially eliminate or reduce pollutants thereon. The second atmosphere is then replaced with a third atmosphere that includes pure, and rapid thermal annealing is performed on the wafer exposed to the third atmosphere in the annealing chamber to substantially reduce the roughness of the free surface of the wafer.
摘要翻译：一种用于降低半导体晶片的自由表面的粗糙度的方法，其包括在退火室中建立第一气氛，用第二气氛代替第一气氛，所述第二气氛包括选择的量和基本上消除或减少污染物的量晶片，并且将晶片的自由表面暴露于第二气氛以基本上消除或减少其上的污染物。然后将第二气氛替换为包括纯的第三气氛，并且在退火室中暴露于第三气氛的晶片上进行快速热退火，以显着降低晶片的自由表面的粗糙度。

28. 发明申请

US20100052092A1 METHOD FOR FABRICATING A SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH REDUCED SECCO DEFECT DENSITY 有权
标题翻译：用于减少SECCO缺陷密度的绝缘体基板上制造半导体的方法
公开(公告)号：US20100052092A1
公开(公告)日：2010-03-04
申请号：US12478063
申请日：2009-06-04
申请人： Luciana Capello , Oleg Kononchuk , Eric Neyret , Alexandra Abbadie , Walter Schwarzenbach
发明人： Luciana Capello , Oleg Kononchuk , Eric Neyret , Alexandra Abbadie , Walter Schwarzenbach
IPC分类号： H01L21/762 , H01L27/12
CPC分类号： H01L21/76254
摘要： The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cm2 the implanting is carried out with a dose of less than 2.3×106 atoms per cm2 and the thinning is an oxidation step conducted at a temperature of less than 925° C.
摘要翻译：本发明涉及一种通过提供源极衬底来制造绝缘体上半导体衬底，特别是绝缘体上硅衬底的方法，通过注入原子种类将源极衬底粘合到源极衬底内，将源极衬底接合到处理衬底上，在预定的分割区域处将源极衬底的剩余部分从源极 - 手柄部件分离，从而将源极衬底的器件层转移到处理衬底上，并使器件层变薄。为了获得具有小于每平方厘米100的Secco缺陷密度降低的半导体绝缘体衬底，以小于2.3×10 6原子/ cm 2的剂量进行注入，并且稀化是在小于925℃的温度下进行的氧化步骤 C。

29. 发明授权

US07666758B2 Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer 有权
标题翻译：用于制造具有薄表面层的绝缘体上硅型衬底的工艺
公开(公告)号：US07666758B2
公开(公告)日：2010-02-23
申请号：US11848964
申请日：2007-08-31
申请人： Eric Neyret
发明人： Eric Neyret
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L21/76259
摘要： A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor substrate to a semiconductor receiver substrate, with one of the substrates including an oxide layer that is present between the donor and receiver substrates after bonding; detaching a remainder of the donor substrate along the weakened zone to obtain a semifinished SOI substrate comprising the receiver substrate, the oxide layer and the thick layer; and finishing the semifinished SOI substrate by thinning the thick layer to obtain a silicon layer having a thickness is less than that of the thick layer but greater than 150 nm; long annealing the semifinished SOI substrate in a gaseous atmosphere comprising hydrogen and/or argon; and thinning the thin layer to obtain an ultrathin layer with a thickness of 150 nm or less and the finished substrate.
摘要翻译：一种通过在半导体施主衬底内形成弱化区以制造厚度大于150nm并形成厚层与供体衬底的其余部分之间的边界的制造绝缘体上硅（SOI）衬底的方法，将施主衬底接合到半导体接收器衬底，其中一个衬底包括在接合之后存在于施主器和接收器衬底之间的氧化物层; 沿着弱化区域分离供体衬底的剩余部分，以获得包含接收衬底，氧化物层和厚层的半成品SOI衬底; 并通过使厚层变薄来完成半成品SOI衬底，以获得厚度小于厚层但大于150nm的硅层; 在包含氢和/或氩的气体气氛中对半成品SOI衬底进行长时间退火; 并使薄层变薄，得到厚度为150nm以下的超薄层和成品基板。

30. 发明申请

US20080188060A1 PROCESS FOR FABRICATING A SUBSTRATE OF THE SILICON-ON-INSULATOR TYPE WITH THIN SURFACE LAYER 有权
标题翻译：用于制造具有薄表面层的绝缘硅绝缘体基板的工艺
公开(公告)号：US20080188060A1
公开(公告)日：2008-08-07
申请号：US11848964
申请日：2007-08-31
申请人： Eric NEYRET
发明人： Eric NEYRET
IPC分类号： H01L21/46
CPC分类号： H01L21/76254 , H01L21/76259
摘要： A process for fabricating a silicon on insulator (SOI) substrate by forming a weakened zone within a semiconductor donor substrate to define a thick layer having a thickness of greater 150 nm and form a boundary between the thick layer and a remainder of the donor substrate, bonding the donor substrate to a semiconductor receiver substrate, with one of the substrates including an oxide layer that is present between the donor and receiver substrates after bonding; detaching a remainder of the donor substrate along the weakened zone to obtain a semifinished SOI substrate comprising the receiver substrate, the oxide layer and the thick layer; and finishing the semifinished SOI substrate by thinning the thick layer to obtain a silicon layer having a thickness is less than that of the thick layer but greater than 150 nm; long annealing the semifinished SOI substrate in a gaseous atmosphere comprising hydrogen and/or argon; and thinning the thin layer to obtain an ultrathin layer with a thickness of 150 nm or less and the finished substrate.
摘要翻译：一种通过在半导体施主衬底内形成弱化区以制造厚度大于150nm并形成厚层与供体衬底的其余部分之间的边界的制造绝缘体上硅（SOI）衬底的方法，将施主衬底接合到半导体接收器衬底，其中一个衬底包括在接合之后存在于施主器和接收器衬底之间的氧化物层; 沿着弱化区域分离供体衬底的剩余部分，以获得包含接收衬底，氧化物层和厚层的半成品SOI衬底; 并通过使厚层变薄来完成半成品SOI衬底，以获得厚度小于厚层但大于150nm的硅层; 在包含氢和/或氩的气体气氛中对半成品SOI衬底进行长时间退火; 并使薄层变薄，得到厚度为150nm以下的超薄层和成品基板。

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