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21. 发明授权

US06751126B2 Clamping circuit and nonvolatile memory device using the same 失效
标题翻译：夹紧电路和使用其的非易失性存储器件
公开(公告)号：US06751126B2
公开(公告)日：2004-06-15
申请号：US10326632
申请日：2002-12-23
申请人： Dae Han Kim
发明人： Dae Han Kim
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C5/145
摘要： The present invention relates to a clamping circuit and a nonvolatile memory device using the same. Each of switching means driven by a gate voltage of a transistor included in a clamping circuit are installed between a drain terminal of the transistor and a terminal of the well in which the transistor is formed. A given bias is applied to the well and the threshold voltage of the transistor is thus lowered. Thus, the operating speed of the transistor can be increased even at a low power supply voltage without additionally using a manufacture process for the low voltage operation. Further, the ripple voltage can be minimized and generation of defect can be thus prevented. As a result, electrical characteristic and reliability of the circuit is improved.
摘要翻译：本发明涉及一种钳位电路和使用该钳位电路的非易失性存储器件。由钳位电路中包括的晶体管的栅极电压驱动的开关装置中的每一个安装在晶体管的漏极端子和形成晶体管的阱的端子之间。给阱提供给定的偏压，因此降低了晶体管的阈值电压。因此，即使在低电源电压下也可以提高晶体管的工作速度，而不需要额外使用低电压工作的制造工艺。此外，纹波电压可以最小化，从而可以防止产生缺陷。结果，提高了电路的电气特性和可靠性。

22. 发明授权

US06292397B1 Nonvolatile memory sensing circuit and techniques thereof 有权
标题翻译：非易失性存储器感测电路及其技术
公开(公告)号：US06292397B1
公开(公告)日：2001-09-18
申请号：US09590071
申请日：2000-06-09
申请人： Dae-Han Kim
发明人： Dae-Han Kim
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5642 , G11C2211/5634
摘要： The nonvolatile memory sensing circuit includes a main cell part and at least one reference cell part, including a main cell array having a plurality of main cells to which a word line driving signal is applied respectively, a plurality of main cell switches receiving a plurality of main cell selection signals YG0 to YGn which switch to select one of the main cells wherein the main cell switches are connected to the main cell array in series, a main cell bit line voltage controller maintaining drain voltage to a fixed level by receiving program bias voltage PRBIAS, a main cell path transistor connected between an output of the main cell bit line voltage controller and internal power supply voltage wherein the main cell path transistor outputting a state of the main cell, and at least one sense amplifier producing a comparison output SAOUT by receiving at least one reference voltage RDREF and an output SENSE of the main cell path transistor, and wherein the reference cell part further comprises a program reference cell part and read reference cell part which share a voltage controlling means regulating drain or source voltage to a predetermined level and wherein the reference cell part produces reference voltage RDREF of fixed level.
摘要翻译：非易失性存储器感测电路包括主单元部分和至少一个参考单元部分，包括分别施加有字线驱动信号的多个主单元的主单元阵列，多个主单元开关，其接收多个主单元选择信号YG0至YGn，其切换以选择其中主单元开关串联连接到主单元阵列的主单元之一;主单元位线电压控制器，通过接收编程偏置电压将漏极电压维持在固定电平 PRBIAS，连接在主单元位线电压控制器的输出和输出主单元的状态的主单元路径晶体管的内部电源电压之间的主单元路径晶体管，以及至少一个读出放大器，其通过以下方式产生比较输出SAOUT：接收主单元路径晶体管的至少一个参考电压RDREF和输出SENSE，并且其中参考单元部分进一步c 具有节目参考单元部分和读取参考单元部分，其共享将电源电压调节到预定电平的电压控制装置，并且其中参考单元部分产生固定电平的参考电压RDREF。

23. 发明授权

US09196364B2 Nonvolatile memory device having split ground selection line structures 有权
标题翻译：具有分割地选择线结构的非易失性存储器件
公开(公告)号：US09196364B2
公开(公告)日：2015-11-24
申请号：US14244930
申请日：2014-04-04
申请人： Minsu Kim , Yang-Lo Ahn , Dae Han Kim , Kitae Park
发明人： Minsu Kim , Yang-Lo Ahn , Dae Han Kim , Kitae Park
IPC分类号： G11C16/04 , G11C16/08 , G11C16/34
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/3427
摘要： A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.
摘要翻译：非易失性存储器件包括以三维（3D）结构排列的多个垂直NAND闪存单元，设置在3D结构中并具有由第一地选择线和第二地选择线选择的存储单元的第一存储块，其中所述第一和第二接地选择线彼此电分离，设置在所述3D结构中并具有由第三选择线和第四选择线选择的存储单元的第二存储器块，其中所述第三和第四接地选择线被电分离以及传递驱动信号以通过响应于块选择信号接通分别连接到第一和第三接地选择线的接地选择晶体管的传输晶体管。

24. 发明授权

US07548466B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07548466B2
公开(公告)日：2009-06-16
申请号：US11521479
申请日：2006-09-15
申请人： Sang-Kug Park , Dae-Han Kim
发明人： Sang-Kug Park , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C11/5621 , G11C16/30
摘要： A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.
摘要翻译：闪存器件包括包括多个存储单元的存储单元阵列。闪速存储装置还包括产生要施加到存储单元阵列的多个恒定电压的电压产生电路，该电压产生电路包括产生至少两个恒定电压的多个电压调节器，每个恒定电压具有恒定的电压差。

25. 发明申请

US20070053228A1 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US20070053228A1
公开(公告)日：2007-03-08
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

26. 发明申请

US20060126387A1 Multi-level cell memory device and associated read method 有权
标题翻译：多级单元存储器件及相关读取方法
公开(公告)号：US20060126387A1
公开(公告)日：2006-06-15
申请号：US11296476
申请日：2005-12-08
申请人： Dae-Han Kim , Seung-Keun Lee
发明人： Dae-Han Kim , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/24
摘要： A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.
摘要翻译： NOR闪存器件包括适于存储至少两位数据的存储器单元。通过产生具有第一幅度的参考电流来对存储器单元执行读取操作，以检测最高有效位（MSB）的值并产生具有第二幅度的参考电流以检测最低有效位（LSB）的值）。通过在读取操作期间将第一和第二参考电流与流过存储器单元的电流量进行比较来检测MSB和LSB的相应值。第一和第二参考电流的相应大小由参考电压发生器产生的不同参考电压确定。

27. 发明授权

US06865116B2 Clamp circuit and boosting circuit using the same 有权
标题翻译：钳位电路和升压电路使用相同
公开(公告)号：US06865116B2
公开(公告)日：2005-03-08
申请号：US10329529
申请日：2002-12-27
申请人： Dae Han Kim , Yi Jin Kwon
发明人： Dae Han Kim , Yi Jin Kwon
IPC分类号： G11C16/06 , G11C5/14 , G11C7/00 , G11C16/30 , H03K5/08 , H03L5/00
CPC分类号： G11C5/145 , H03K5/08
摘要： The present invention relates to a clamp circuit and a boosting circuit using the same. In order to drop a boosting voltage to a target word line voltage, at least one or more clamp circuit is provided. At least one or more of the clamp circuits are independently driven in a desired sensing period to lower the boosting voltage. Thus, rapid read access time is accomplished upon a data read operation. Current consumption can be minimized and a stabilized word line voltage can be generated.
摘要翻译：本发明涉及一种钳位电路和使用该钳位电路的升压电路。为了将升压电压降低到目标字线电压，提供至少一个或多个钳位电路。至少一个或多个钳位电路在期望的感测周期中被独立地驱动以降低升压电压。因此，快速读取访问时间是在数据读取操作时完成的。可以使电流消耗最小化，并且可以产生稳定的字线电压。

28. 发明授权

US06704225B2 Sensing circuit for nonvolatile memory device 失效
标题翻译：非易失性存储器件的感应电路
公开(公告)号：US06704225B2
公开(公告)日：2004-03-09
申请号：US10028694
申请日：2001-12-28
申请人： Dae-Han Kim
发明人： Dae-Han Kim
IPC分类号： G11C1606
CPC分类号： G11C16/26 , G11C16/28
摘要： A sensing circuit of a non-volatile memory device comprises a regulation unit, a DTMOS transistor, a first NMOS transistor, a second NMOS transistor and a sense amplifier. The sensing circuit of the present invention eliminates the threshold voltage on the high voltage transistor; therefore, the sensing circuit prevents gate oxide breakdown, makes it possible to drive the sensing circuit using a low voltage, and increases processing speed by improving transconductance.
摘要翻译：非易失性存储器件的感测电路包括调节单元，DTMOS晶体管，第一NMOS晶体管，第二NMOS晶体管和读出放大器。本发明的检测电路消除了高电压晶体管上的阈值电压; 因此，感测电路防止栅极氧化物击穿，使得可以使用低电压驱动感测电路，并且通过改善跨导来提高处理速度。

29. 发明授权

US06545917B2 Circuit for clamping word-line voltage 失效
标题翻译：用于钳位字线电压的电路
公开(公告)号：US06545917B2
公开(公告)日：2003-04-08
申请号：US10006112
申请日：2001-12-10
申请人： Dae Han Kim
发明人： Dae Han Kim
IPC分类号： G11C700
CPC分类号： G11C8/08
摘要： The present invention relates to a circuit for clamping a word line voltage. The circuit comprises a reference voltage generating means for generating a reference voltage depending on first and second signals; a bootstrap circuit for generating a pumping voltage of a higher potential than a target voltage depending on the first and second signals to an output terminal; a control signal generating means for generating the first and second control signals depending on the first˜third signals; a clamping control means for falling the pumping voltage depending the first and second control signals to generate a compare voltage; a comparator for comparing the reference voltage and the compare voltage to generate a third signal; and a discharging means for discharging the potential of the output terminal depending on the third signal to fall the pumping voltage to a target voltage.
摘要翻译：本发明涉及一种用于钳位字线电压的电路。电路包括用于根据第一和第二信号产生参考电压的参考电压产生装置; 引导电路，用于根据第一和第二信号产生比目标电压更高的电压的泵浦电压到输出端子; 控制信号发生装置，用于根据第一至第三信号产生第一和第二控制信号; 钳位控制装置，用于根据第一和第二控制信号降低泵浦电压以产生比较电压; 用于比较参考电压和比较电压以产生第三信号的比较器; 以及放电装置，用于根据第三信号放电输出端子的电位，以将泵浦电压降低到目标电压。

30. 发明授权

US08238160B2 Nonvolatile memory device and memory system having the same 有权
标题翻译：非易失性存储器件和具有相同的存储器系统
公开(公告)号：US08238160B2
公开(公告)日：2012-08-07
申请号：US12639119
申请日：2009-12-16
申请人： Soo-Han Kim , Dae Han Kim
发明人： Soo-Han Kim , Dae Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26
摘要： A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.
摘要翻译：一种非易失性存储器件，包括具有布置在字线和位线的交点处的存储单元的单元阵列; 地址解码器，被配置为响应于地址选择一条字线; 写入电路，被配置为将程序数据写入与所选择的字线连接的存储器单元中; 以及控制电路，被配置为控制地址解码器和写入电路，使得在写入操作期间顺序地执行多个频带程序（写入）操作，其中所述控制电路还被配置为选择每个频带写入操作的最佳写入条件的下一个频带写操作。多个可用写入条件作为修剪信息存储在多个寄存器中。控制电路选择用于在最佳写入条件下进行编程的寄存器存储信息。

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