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21. 发明申请

US20080142798A1 SEMICONDUCTOR WAFER 有权
公开(公告)号：US20080142798A1
公开(公告)日：2008-06-19
申请号：US11758639
申请日：2007-06-05
申请人： Chien-Li Kuo , Ping-Chang Wu , Jui-Meng Jao , Hui-Ling Chen , Kai-Kuang Ho , Ching-Li Yang
发明人： Chien-Li Kuo , Ping-Chang Wu , Jui-Meng Jao , Hui-Ling Chen , Kai-Kuang Ho , Ching-Li Yang
IPC分类号： H01L23/58 , H01L23/544
CPC分类号： H01L23/544 , H01L22/34 , H01L23/562 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.
摘要翻译：半导体晶片包括多个管芯区域，至少第一划线区域和围绕每个管芯区域的至少第二划线区域，至少位于第一划线区域中的第一金属结构，以及至少第二金属结构位于第二划线区域。第一金属结构包括平行于第一划线区域的至少第一槽，或包括以阵列布置的多个开口。第二金属结构包括平行于第二划线区域的至少第二槽，或包括以阵列布置的多个开口。

22. 发明授权

US07387950B1 Method for forming a metal structure 有权
标题翻译：金属结构的形成方法
公开(公告)号：US07387950B1
公开(公告)日：2008-06-17
申请号：US11611888
申请日：2006-12-17
申请人： Chien-Li Kuo , Ping-Chang Wu , Jui-Meng Jao , Hui-Ling Chen , Kai-Kuang Ho , Ching-Li Yang
发明人： Chien-Li Kuo , Ping-Chang Wu , Jui-Meng Jao , Hui-Ling Chen , Kai-Kuang Ho , Ching-Li Yang
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L23/544 , H01L22/34 , H01L23/562 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.
摘要翻译：半导体晶片包括多个管芯区域，至少第一划线区域和围绕每个管芯区域的至少第二划线区域，至少位于第一划线区域中的第一金属结构，以及至少第二金属结构位于第二划线区域。第一金属结构包括平行于第一划线区域的至少第一槽，或包括以阵列布置的多个开口。第二金属结构包括平行于第二划线区域的至少第二槽，或包括以阵列布置的多个开口。

23. 发明申请

US20070290204A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070290204A1
公开(公告)日：2007-12-20
申请号：US11309062
申请日：2006-06-15
申请人： Jui-Meng Jao , Chien-Li Kuo , Hui-Ling Chen , Pao-Chuan Chen
发明人： Jui-Meng Jao , Chien-Li Kuo , Hui-Ling Chen , Pao-Chuan Chen
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L24/02 , H01L2924/01019
摘要： The invention is directed to a semiconductor structure located on a substrate in a scribe line region of a wafer. The semiconductor structure comprises a first dielectric layer, a first test pad and a passivation layer. The first dielectric layer is disposed on the substrate and the first test pad is disposed on the first dielectric layer. The passivation layer is disposed on the first dielectric layer and surrounding the first test pad and a groove is located between the first test pad and the passivation layer and the groove is at lest located between the boundary of the scribe line region and the first test pad.
摘要翻译：本发明涉及位于晶片的划线区域中的衬底上的半导体结构。半导体结构包括第一介电层，第一测试焊盘和钝化层。第一电介质层设置在基板上，第一测试焊盘设置在第一电介质层上。钝化层设置在第一电介质层上并围绕第一测试焊盘，并且沟槽位于第一测试焊盘和钝化层之间，并且槽至少位于划线区域的边界和第一测试焊盘之间。

24. 发明申请

US20070238244A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070238244A1
公开(公告)日：2007-10-11
申请号：US11279254
申请日：2006-04-11
申请人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
发明人： Yung-Chang Lin , Sun-Chieh Chien , Chien-Li Kuo , Ruey-Chyr Lee
IPC分类号： H01L21/8242 , H01L21/336 , H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor structure includes a semiconductor substrate comprising thereon a STI structure. A capacitor deep trench is etched into the semiconductor substrate. Collar oxide layer is disposed on inner surface of the capacitor deep trench. A first doped polysilicon layer is disposed on the collar oxide layer and on the exposed bottom of the capacitor deep trench. A capacitor dielectric layer is formed on the first doped polysilicon layer. A second doped polysilicon layer is formed on the capacitor dielectric layer. A deep ion well is formed in the semiconductor substrate, wherein the deep ion well is electrically connected with the first doped polysilicon layer through the bottom of the capacitor deep trench. A passing gate insulation (PGI) layer is formed on the second doped polysilicon layer and on the STI structure.
摘要翻译：沟槽电容器结构包括其上包括STI结构的半导体衬底。电容器深沟槽被蚀刻到半导体衬底中。环状氧化物层设置在电容器深沟槽的内表面上。第一掺杂多晶硅层设置在轴环氧化物层和电容器深沟槽的暴露的底部上。在第一掺杂多晶硅层上形成电容器电介质层。第二掺杂多晶硅层形成在电容器介电层上。在半导体衬底中形成深离子阱，其中深离子阱通过电容器深沟槽的底部与第一掺杂多晶硅层电连接。在第二掺杂多晶硅层和STI结构上形成通过栅极绝缘（PGI）层。

25. 发明授权

US06727180B2 Method for forming contact window 有权
标题翻译：形成接触窗的方法
公开(公告)号：US06727180B2
公开(公告)日：2004-04-27
申请号：US09839365
申请日：2001-04-23
申请人： Chien-Li Kuo , Wei-Wu Liao
发明人： Chien-Li Kuo , Wei-Wu Liao
IPC分类号： H01L21301
CPC分类号： H01L21/76804
摘要： A method for forming contact window is disclosed. Essential concept of the invention comprises over coating layer formed over surface before forming contact window is formed and the etching rate of over coating layer is higher than etching rate of underlying layer. The method comprises following steps: First, forming semiconductor structures on surface of wafer. Second, forming a coating layer over the surface and covering these semiconductor structures. Third, forming an over coating layer on the coating layer, where etching rate of over coating layer is higher than etching rate of coating layer. Finally, form contact window with outwardly winded shape. Thus, contact window formed by the invention is more convenient for filling material than contact window formed by conventional method. In addition, because width of contact window is not obviously increased, this invention is more beneficial for deep-submicron fabrication.
摘要翻译：公开了一种形成接触窗的方法。本发明的基本概念包括在形成接触窗形成之前在表面上形成的覆盖层，并且过涂层的蚀刻速率高于下层的蚀刻速率。该方法包括以下步骤：首先在晶片表面形成半导体结构。其次，在表面上形成覆盖层并覆盖这些半导体结构。第三，在涂层上形成过涂层，其中涂层的蚀刻速率高于涂层的蚀刻速率。最后，形成具有向外缠绕形状的接触窗。因此，本发明形成的接触窗比常规方法形成的接触窗更容易填充材料。此外，由于接触窗宽度不明显增加，本发明对深亚微米制造更有利。

26. 发明授权

US06468838B2 Method for fabricating a MOS transistor of an embedded memory 有权
标题翻译：一种用于制造嵌入式存储器的MOS晶体管的方法
公开(公告)号：US06468838B2
公开(公告)日：2002-10-22
申请号：US09798857
申请日：2001-03-01
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L21335
CPC分类号： H01L21/823814 , H01L27/105 , H01L27/1052
摘要： The present invention provides a method for manufacturing a MOS transistor of an embedded memory on the surface of semiconductor wafer. The method of present invention is first to define a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to depose a dielectric layer, a undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a photoresist layer sequentially. Next, a plurality of gate patterns on the memory array area is defined and the protection layer is etched to the surface of the doped polysilicon layer. Then a plurality of gate patterns on the periphery circuit region is defined in and the doped polysilicon layer, the silicide layer and the undoped polysilicon layer are etched to the surface of the dielectric layer so as to form gates of each MOS transistors in the memory array area and periphery circuit region. Finally a spacer and source and drain region are formed around each gate.
摘要翻译：本发明提供一种在半导体晶片的表面上制造嵌入式存储器的MOS晶体管的方法。本发明的方法首先是在半导体晶片的表面上限定存储器阵列区域和外围电路区域，并且去除介质层，未掺杂多晶硅层，硅化物层，掺杂多晶硅层，保护层和光致抗蚀剂层。接下来，限定存储器阵列区域上的多个栅极图案，并且将保护层蚀刻到掺杂多晶硅层的表面。然后，限定外围电路区域上的多个栅极图案，并且将掺杂多晶硅层，硅化物层和未掺杂的多晶硅层蚀刻到电介质层的表面，以形成存储器阵列中的每个MOS晶体管的栅极区域和外围电路区域。最后，围绕每个栅极形成间隔物和源极和漏极区。

27. 发明授权

US06436759B1 Method for fabricating a MOS transistor of an embedded memory 有权
标题翻译：一种用于制造嵌入式存储器的MOS晶体管的方法
公开(公告)号：US06436759B1
公开(公告)日：2002-08-20
申请号：US09764330
申请日：2001-01-19
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L218247
CPC分类号： H01L27/105 , H01L21/823835 , H01L21/823842 , H01L27/10873 , H01L27/10894 , Y10S438/981
摘要： A memory array area and a periphery circuit region on the surface of a semiconductor wafer are defined, and a gate oxide layer and an undoped polysilicon layer are sequentially formed on the wafer. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer, followed by etching of the doped polysilicon layer in the memory array area down to a predetermined thickness. Next, a silicide layer and a protection layer are formed on the surface of the semiconductor wafer. A photo-etching-process (PEP) is used to etch portions of the protection layer, the silicide layer, the undoped polysilicon layer and the doped polysilicon layer to form a plurality of gates. Finally, a LDD and spacers of each MOS transistor, and a source and a drain of each MOS transistor in the periphery circuit region are formed.
摘要翻译：定义半导体晶片表面上的存储器阵列区域和外围电路区域，并且在晶片上依次形成栅极氧化物层和未掺杂的多晶硅层。接下来，将存储器阵列区域中的未掺杂多晶硅层注入以形成掺杂多晶硅层，随后将存储器阵列区域中的掺杂多晶硅层刻蚀成预定厚度。接下来，在半导体晶片的表面上形成硅化物层和保护层。光蚀刻工艺（PEP）用于蚀刻保护层，硅化物层，未掺杂多晶硅层和掺杂多晶硅层的部分以形成多个栅极。最后，形成每个MOS晶体管的LDD和间隔物，以及外围电路区域中的每个MOS晶体管的源极和漏极。

28. 发明授权

US06406971B1 Fabrication method for an embedded dynamic random access memory (DRAM) 失效
标题翻译：嵌入式动态随机存取存储器（DRAM）的制造方法
公开(公告)号：US06406971B1
公开(公告)日：2002-06-18
申请号：US09799909
申请日：2001-03-06
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/76802 , H01L27/10814 , H01L27/10888
摘要： The invention describes an embedded dynamic random access memory (DRAM) fabrication method. After several landing pads in the memory cell region of a substrate have been formed, a bit-line contact opening and first contact opening are formed simultaneously. The bit-line contact opening exposes the landing pad and the first contact opening exposes the NMOS of the periphery circuit region. An N-type ion implantation is performed to implant N-type ions into the landing pad the NMOS. After a bit-line contact, a first contact, and a bit-line have been formed, a storage node contact opening and a second contact opening are formed simultaneously. The storage node contact opening exposes another landing pad and the second contact opening exposes a P-type MOS in the periphery circuit region. A P-type ion implantation step is conducted to implant P-type ions into the landing pad and the PMOS exposed by the second contact opening. A storage node contact is formed in the storage node contact opening and a second contact is formed in the second contact opening. A capacitor is formed that is electrically connected to the storage node contact.
摘要翻译：本发明描述了一种嵌入式动态随机存取存储器（DRAM）制造方法。在基板的存储单元区域中形成几个着陆焊盘之后，同时形成位线接触开口和第一接触开口。位线接触开口暴露了着陆焊盘，并且第一接触开口暴露了外围电路区域的NMOS。执行N型离子注入以将N型离子注入到着陆焊盘中。在位线接触之后，已经形成第一接触和位线，同时形成存储节点接触开口和第二接触开口。存储节点接触开口暴露另一个着陆焊盘，第二接触开口露出外围电路区域中的P型MOS。进行P型离子注入步骤以将P型离子注入到着陆焊盘和由第二接触开口暴露的PMOS。存储节点接触件形成在存储节点接触开口中，并且第二接触件形成在第二接触开口中。形成电连接到存储节点接点的电容器。

29. 发明授权

US06403417B1 Method for in-situ fabrication of a landing via and a strip contact in an embedded memory 有权
标题翻译：在嵌入式存储器中原位制造着陆通道和带状接触件的方法
公开(公告)号：US06403417B1
公开(公告)日：2002-06-11
申请号：US09803881
申请日：2001-03-13
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L218242
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823418 , H01L21/823481 , H01L27/1052 , H01L27/10873 , H01L27/10894
摘要： The present invention provides a method to integrate the process of manufacturing an embedded memory and the sequential process of forming a landing via and a strip contact in the embedded memory. The method involves first defining a memory array region and a periphery circuit region on the surface of a silicon substrate of a semiconductor wafer. Next, a plurality of gates and lightly doped drains are separately formed in the memory array region and the periphery circuit region. A silicon nitride layer then covers the surface of each gate in the memory array region, and forms a spacer on either side of each gate in the periphery circuit region. Then, a dielectric layer is formed on the surface of the semiconductor wafer, and a landing via hole and a strip contact hole are separately formed in the dielectric layer in the memory array region and the periphery circuit region, respectively. Finally, each hole is filled with a conductive layer to form in-situ each landing via and strip contact.
摘要翻译：本发明提供了一种将嵌入式存储器的制造过程与在嵌入式存储器中形成层叠通孔和条形接触的顺序处理相集成的方法。该方法包括首先在半导体晶片的硅衬底的表面上限定存储器阵列区域和外围电路区域。接下来，在存储器阵列区域和外围电路区域中分别形成多个栅极和轻掺杂漏极。然后，氮化硅层覆盖存储器阵列区域中的每个栅极的表面，并且在外围电路区域中的每个栅极的任一侧上形成间隔物。然后，在半导体晶片的表面上形成电介质层，分别在存储器阵列区域和外围电路区域的电介质层中形成层叠通路孔和带状接触孔。最后，每个孔填充有导电层，以便原位形成每个着陆通路和带状接触。

30. 发明授权

US06395596B1 Method of fabricating a MOS transistor in an embedded memory 有权
标题翻译：在嵌入式存储器中制造MOS晶体管的方法
公开(公告)号：US06395596B1
公开(公告)日：2002-05-28
申请号：US09819751
申请日：2001-03-29
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L218247
CPC分类号： H01L27/10894 , H01L21/823418 , H01L21/823468 , H01L27/1052 , H01L27/10873
摘要： The present invention provides a method of fabricating a MOS transistor in an embedded memory. A first dielectric layer, an undoped polysilicon layer, and a second dielectric layer are formed on the periphery circuits area. Next, the undoped polysilicon layer in the memory array area is doped, followed by removal of the second dielectric layer in the memory array area. Then, a silicide layer and a protective layer are formed and portions of the memory array area are etched to form gates. LDDs in each MOS transistor in the memory array area are formed. Next, LDDs in each MOS transistor in the periphery circuits area are formed. A portion of the silicon nitride layer and the silicon oxide layer in the periphery circuits area form a spacer on either side of each gate in the periphery circuits area. Finally, a source and drain (S/D) are formed in the periphery circuits area.
摘要翻译：本发明提供一种在嵌入式存储器中制造MOS晶体管的方法。在外围电路区域上形成第一电介质层，未掺杂多晶硅层和第二电介质层。接下来，对存储器阵列区域中的未掺杂的多晶硅层进行掺杂，然后去除存储器阵列区域中的第二介质层。然后，形成硅化物层和保护层，并且蚀刻存储器阵列区域的一部分以形成栅极。形成存储器阵列区域中的每个MOS晶体管中的LDD。接下来，形成外围电路区域中的每个MOS晶体管中的LDD。外围电路区域中的氮化硅层和氧化硅层的一部分在外围电路区域中的每个栅极的任一侧上形成间隔物。最后，在外围电路区域形成源极和漏极（S / D）。

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