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21. 发明授权

US08432032B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08432032B2
公开(公告)日：2013-04-30
申请号：US12687093
申请日：2010-01-13
申请人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
发明人： Chia-Sheng Lin , Chia-Lun Tsai , Chang-Sheng Hsu , Po-Han Lee
IPC分类号： H01L23/48
CPC分类号： H01L24/73 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/29 , H01L24/94 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3512 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.
摘要翻译：提供了芯片封装及其制造方法。芯片封装包括具有第一表面和相对的第二表面的半导体衬底。在第一表面上形成有从第一表面延伸到第二表面的通孔。导电迹线层形成在第一表面和通孔中。在通孔中形成缓冲塞，在第一表面和通孔中形成保护层。

22. 发明授权

US08384222B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08384222B2
公开(公告)日：2013-02-26
申请号：US13030887
申请日：2011-02-18
申请人： Chia-Lun Tsai , Ching-Yu Ni , Jack Chen , Wen-Cheng Chien
发明人： Chia-Lun Tsai , Ching-Yu Ni , Jack Chen , Wen-Cheng Chien
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05548 , H01L2224/05644 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.
摘要翻译：公开了一种半导体器件及其制造方法。该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。半导体管芯包括在其活性表面中暴露的顶部金属。钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

23. 发明授权

US08284296B2 Continuous focusing method for digital camera 有权
标题翻译：数码相机连续对焦方式
公开(公告)号：US08284296B2
公开(公告)日：2012-10-09
申请号：US12772458
申请日：2010-05-03
申请人： Chan-Min Chou , Chia-Lun Tsai , Chih-Pin Yen
发明人： Chan-Min Chou , Chia-Lun Tsai , Chih-Pin Yen
IPC分类号： H04N5/232 , H04N5/228 , G03B13/00
CPC分类号： H04N5/23212 , H04N5/23241
摘要： A continuous focusing method for a digital camera is described, which is applicable to determine whether the digital camera performs a focusing procedure or not when the digital camera switches from a first scene to a second scene in a live view stage. The continuous focusing method includes the following steps. A preview image of a second scene is obtained. A blur detection procedure is performed on the preview image, so as to acquire a corresponding focus value. It is determined whether the focus value exceeds a focusing threshold value or not; if not, a focusing procedure is performed; otherwise, if the focus value is greater than the focusing threshold value, the digital camera still maintains a current focusing focal length, which represents that a focusing focal length of the second scene is the same as that of the first scene.
摘要翻译：描述了用于数字照相机的连续聚焦方法，其可应用于当数字照相机在实时显示阶段从第一场景切换到第二场景时，确定数字照相机是否执行聚焦程序。连续聚焦方法包括以下步骤。获得第二场景的预览图像。对预览图像执行模糊检测过程，以获得相应的聚焦值。确定焦点值是否超过聚焦阈值; 如果不是，则进行聚焦过程; 否则，如果聚焦值大于聚焦阈值，则数字照相机仍保持当前聚焦焦距，其表示第二场景的聚焦焦距与第一场景相同。

24. 发明申请

US20110140267A1 ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电子设备包装及其制造方法
公开(公告)号：US20110140267A1
公开(公告)日：2011-06-16
申请号：US12849089
申请日：2010-08-03
申请人： Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人： Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译：本发明提供一种电子器件封装及其制造方法。电子器件封装包括载体晶片。具有多个导电焊盘的电子器件芯片设置在载体晶片上。隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。隔离层压层具有多个开口以露出导电垫。在隔离层压层和开口中顺应地形成多个再分配图案。再分布图案分别电连接到导电焊盘。多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

25. 发明申请

US20110079892A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110079892A1
公开(公告)日：2011-04-07
申请号：US12896277
申请日：2010-10-01
申请人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
发明人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L21/78 , H01L21/76898 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/92 , H01L24/94 , H01L2224/023 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13024 , H01L2224/2919 , H01L2224/73253 , H01L2224/9202 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2224/03 , H01L2224/11 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
摘要翻译：芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

26. 发明申请

US20090289273A1 LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF 有权
标题翻译：发光装置包装结构及其制造方法
公开(公告)号：US20090289273A1
公开(公告)日：2009-11-26
申请号：US12471255
申请日：2009-05-22
申请人： Chia-Lun Tsai , Ching-Yu Ni , Wen-Cheng Chien , Shang-Yi Wu , Cheng-Te Chou
发明人： Chia-Lun Tsai , Ching-Yu Ni , Wen-Cheng Chien , Shang-Yi Wu , Cheng-Te Chou
IPC分类号： H01L33/00
CPC分类号： H01L33/385 , H01L33/62 , H01L33/64 , H01L33/642 , H01L2924/0002 , H01L2924/00
摘要： A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.
摘要翻译：描述了发光器件封装结构。发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。基板和发光元件芯片分别具有芯片侧和基板侧。第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

27. 发明申请

US20080191205A1 Test structure for seal ring quality monitor 有权
标题翻译：密封圈质量监测仪的测试结构
公开(公告)号：US20080191205A1
公开(公告)日：2008-08-14
申请号：US11706940
申请日：2007-02-13
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L24/11 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/45147 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
摘要翻译：半导体结构包括与半导体芯片的边缘相邻的菊花链。菊花链包括分布在多个金属化层中的多个水平金属线，其中水平金属线串联连接; 在相同层中的多个连接焊盘并且电连接水平金属线，其中连接焊盘在物理上彼此分离; 以及多个垂直金属线，每个将所述连接焊盘中的一个连接到所述水平金属线之一，其中所述多个连接焊盘中的一个连接焊盘中的一个连接焊盘仅通过所述多个垂直金属线中的一个垂直连接金属线以及与菊花链相邻且电气断开的密封环。

28. 发明申请

US20070132059A1 Laser fuse with efficient heat dissipation 有权
标题翻译：激光熔丝具有高效散热
公开(公告)号：US20070132059A1
公开(公告)日：2007-06-14
申请号：US11299999
申请日：2005-12-12
申请人： Hao-Yi Tsai , Chao-Hsiang Yang , Shang-Yun Hou , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Chao-Hsiang Yang , Shang-Yun Hou , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.
摘要翻译：提供了具有有效的热路径的半导体结构及其形成方法。半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。保护环通过触点热耦合到半导体衬底。半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

29. 发明授权

US08541877B2 Electronic device package and method for fabricating the same 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US08541877B2
公开(公告)日：2013-09-24
申请号：US12849089
申请日：2010-08-03
申请人： Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人： Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号： H01L23/48
CPC分类号： H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译：本发明提供一种电子器件封装及其制造方法。电子器件封装包括载体晶片。具有多个导电焊盘的电子器件芯片设置在载体晶片上。隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。隔离层压层具有多个开口以露出导电垫。在隔离层压层和开口中顺应地形成多个再分配图案。再分布图案分别电连接到导电焊盘。多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

30. 发明授权

US08524241B2 Fusion proteins comprising a fragment of Vibrio cholerae exotoxin A 有权
标题翻译：包含霍乱弧菌外毒素A片段的融合蛋白
公开(公告)号：US08524241B2
公开(公告)日：2013-09-03
申请号：US12669712
申请日：2008-07-18
申请人： Brian Seed , Jia Liu Wolfe , Chia-Lun Tsai
发明人： Brian Seed , Jia Liu Wolfe , Chia-Lun Tsai
IPC分类号： C07K19/00 , C07K14/28 , C12P21/00 , C12N15/31 , C07H21/04
CPC分类号： C07K14/28
摘要： The invention features recombinant exotoxins from Vibrio cholerae are for the therapeutic treatment of a variety of human diseases, particularly diseases characterized by an abundance or excess of undesired cells.
摘要翻译：本发明特征在于来自霍乱弧菌的重组外毒素用于治疗各种人类疾病，特别是以不希望的细胞丰度或过量为特征的疾病。

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