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1. 发明授权

US08866268B2 Semiconductor package structure and manufacturing method thereof 有权
标题翻译：半导体封装结构及其制造方法
公开(公告)号：US08866268B2
公开(公告)日：2014-10-21
申请号：US13183446
申请日：2011-07-15
申请人： Shang-Yi Wu , Wen-Cheng Chien , Chia-Lun Tsai , Tien-Hao Huang
发明人： Shang-Yi Wu , Wen-Cheng Chien , Chia-Lun Tsai , Tien-Hao Huang
IPC分类号： H01L29/41 , H01L21/283 , H01L23/367 , H01L33/64 , H01L23/00 , H01L33/44 , H01L23/13 , H01L23/498 , H01L23/31
CPC分类号： H01L23/3677 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L24/24 , H01L24/48 , H01L24/82 , H01L33/44 , H01L33/642 , H01L2224/2401 , H01L2224/2405 , H01L2224/24101 , H01L2224/24247 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/73277 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/141 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/15311 , H01L2924/15787 , H01L2933/0075 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.
摘要翻译：提供半导体封装结构及其制造方法。半导体封装结构包括半导体管芯，导热膜，衬底，多个导电膜图案和至少一个绝缘体。导热膜设置在半导体管芯的底部。衬底基本上由导电材料或半导体材料构成。此外，第一孔设置在基板上并通过基板，并且半导体管芯设置在第一孔中。导电膜图案设置在基板上，并且不彼此接触。此外，绝缘体连接在半导体管芯和衬底之间。

2. 发明授权

US08399963B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08399963B2
公开(公告)日：2013-03-19
申请号：US12896277
申请日：2010-10-01
申请人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
发明人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
IPC分类号： H01L23/544 , H01L23/48
CPC分类号： H01L21/78 , H01L21/76898 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/92 , H01L24/94 , H01L2224/023 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13024 , H01L2224/2919 , H01L2224/73253 , H01L2224/9202 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2224/03 , H01L2224/11 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
摘要翻译：芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

3. 发明授权

US08233787B2 Focus method and photographic device using the method 失效
标题翻译：聚焦方法和摄影装置采用该方法
公开(公告)号：US08233787B2
公开(公告)日：2012-07-31
申请号：US12963760
申请日：2010-12-09
申请人： Chih-Pin Yen , Chia-Lun Tsai , Li-Wen Kuo
发明人： Chih-Pin Yen , Chia-Lun Tsai , Li-Wen Kuo
IPC分类号： G03B17/00 , G03B3/00 , G03B13/00 , H04N5/262 , H04N2/232 , G02B7/04
CPC分类号： G03B3/10 , G03B13/34 , G03B13/36
摘要： A photographic device using a focus method includes a zoom lens, an image analyzing module, a focus distance providing module and a processing module. The zoom lens is used for capturing image information of a plurality of positions. The image analyzing module is used for analyzing contrast values of the image information of the plurality of positions. The focus distance providing module is used for providing a non-equivalent and a constant focus distance interval for capturing the image information of the plurality of positions. The processing module is electrically connected with the zoom lens, the image analyzing module, and the focus distance providing module. Whereby, the photographic device acquires the image information of the plurality of positions by the non-equivalent focus distance interval, acquires a coarse focus position, and acquires an accurate focus position by the constant focus distance according to the coarse focus position.
摘要翻译：使用聚焦方法的摄影装置包括变焦镜头，图像分析模块，对焦距离提供模块和处理模块。变焦镜头用于拍摄多个位置的图像信息。图像分析模块用于分析多个位置的图像信息的对比度值。聚焦距离提供模块用于提供用于捕获多个位置的图像信息的非等效和恒定焦距距离间隔。处理模块与变焦镜头，图像分析模块和对焦距离提供模块电连接。由此，拍摄装置通过非等效对焦距离间隔获取多个位置的图像信息，获取粗略聚焦位置，并且通过根据粗焦点位置的恒定焦距来获取准确的聚焦位置。

4. 发明申请

US20090289345A1 ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US20090289345A1
公开(公告)日：2009-11-26
申请号：US12470255
申请日：2009-05-21
申请人： Chia-Lun TSAI , Wen-Cheng CHIEN , Po-Han LEE , Wei-Ming CHEN
发明人： Chia-Lun TSAI , Wen-Cheng CHIEN , Po-Han LEE , Wei-Ming CHEN
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.
摘要翻译：提供一种电子器件封装及其制造方法。制造方法包括提供含有多个具有第一表面和相对的第二表面的芯片的半导体衬底。多个导电电极设置在第一表面上，并且两个相邻芯片的导电电极沿着芯片的侧面方向非对称地布置。在每个芯片中，与芯片侧面形成多个接触孔，以露出导电电极。

5. 发明申请

US20090283877A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090283877A1
公开(公告)日：2009-11-19
申请号：US12466656
申请日：2009-05-15
申请人： Chia-Lun Tsai , Ching-Yu Ni , Jack Chen , Wen-Cheng Chien
发明人： Chia-Lun Tsai , Ching-Yu Ni , Jack Chen , Wen-Cheng Chien
IPC分类号： H01L23/552 , H01L23/532 , H01L21/768
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05548 , H01L2224/05644 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.
摘要翻译：公开了一种半导体器件及其制造方法。该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。半导体管芯包括在其活性表面中暴露的顶部金属。钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

6. 发明申请

US20070224794A1 Single passivation layer scheme for forming a fuse 有权
标题翻译：用于形成保险丝的单个钝化层方案
公开(公告)号：US20070224794A1
公开(公告)日：2007-09-27
申请号：US11390951
申请日：2006-03-27
申请人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L24/11 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14
摘要： An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness and acts as a remaining oxide, and no further remaining passivation layer exists on the ARC.
摘要翻译：提供一种包括熔丝的集成电路结构及其形成方法。集成电路结构包括衬底，衬底上的互连结构，连接到互连结构的熔丝以及熔丝上的抗反射涂层（ARC）。 ARC具有增加的厚度并用作剩余氧化物，并且ARC上不存在进一步的剩余钝化层。

7. 发明授权

US08519512B2 Test line placement to improve die sawing quality 有权
公开(公告)号：US08519512B2
公开(公告)日：2013-08-27
申请号：US11525575
申请日：2006-09-22
申请人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
发明人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L21/782 , H01L21/784 , H01L21/786 , H01L22/10 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

8. 发明授权

US08410599B2 Power MOSFET package 有权
标题翻译：功率MOSFET封装
公开(公告)号：US08410599B2
公开(公告)日：2013-04-02
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L23/04
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译：功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二，并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

9. 发明授权

US08259217B2 Fast focusing method for digital camera 有权
标题翻译：数码相机快速聚焦方法
公开(公告)号：US08259217B2
公开(公告)日：2012-09-04
申请号：US12784762
申请日：2010-05-21
申请人： Chan-Min Chou , Chia-Lun Tsai , Chih-Pin Yen
发明人： Chan-Min Chou , Chia-Lun Tsai , Chih-Pin Yen
IPC分类号： H04N5/232
CPC分类号： G03B13/36 , G06K9/00228 , G06K9/3233 , H04N5/23212 , H04N5/23219
摘要： A fast focusing method for a digital camera is applied in an auto focusing stage for judging whether the digital camera needs to be refocused. The fast focusing method includes recording a system time after a previous focusing (defined as a first time); capturing a system time before a current focusing (defined as a second time); performing a fuzziness detection procedure to acquire a focus value when a difference obtained by subtracting the first time from the second time is greater than a focusing time threshold; setting a focusing focal length range covering a reference focal length when the focus value is between a lower limit focusing threshold and an upper limit focusing threshold; capturing images at different focusing focal lengths respectively in the focusing focal length range; calculating a contrast value of each image; calculating a target focal length from the contrast values through a quadratic curve approximation method.
摘要翻译：用于数码相机的快速聚焦方法被应用于自动对焦阶段，用于判断数码相机是否需要重新聚焦。快速聚焦方法包括在先前聚焦（定义为第一次）之后记录系统时间; 在当前对焦之前捕获系统时间（定义为第二次）; 当通过从第二时间减去第一次获得的差大于聚焦时间阈值时，执行模糊检测过程以获取聚焦值; 当聚焦值在下限聚焦阈值和上限聚焦阈值之间时，设置覆盖参考焦距的聚焦焦距范围; 在聚焦焦距范围内分别拍摄不同聚焦焦距的图像; 计算每个图像的对比度值; 通过二次曲线近似法从对比度值计算目标焦距。

10. 发明申请

US20120008038A1 ASSISTING FOCUSING METHOD FOR FACE BLOCK 有权
标题翻译：辅助面部聚焦方法
公开(公告)号：US20120008038A1
公开(公告)日：2012-01-12
申请号：US12833377
申请日：2010-07-09
申请人： Chih Pin Yen , Chia Lun Tsai , Li Wen Kuo
发明人： Chih Pin Yen , Chia Lun Tsai , Li Wen Kuo
IPC分类号： H04N5/232 , G03B13/00
CPC分类号： G03B13/36 , G03B3/10 , H04N5/23212 , H04N5/23219
摘要： An assisting focusing method is applicable in an image capture device having an auto focusing (AF) procedure. The AF procedure has a preset sampling interval. The assisting focusing method includes the following steps. An image for focusing is captured. A face parameter of a face block in the image for focusing is calculated. According to the face parameter, a parameter-to-focus conversion table is looked up to acquire a focusing section. According to the focusing section and a face sampling interval, the AF procedure is performed to acquire a target focus. The face sampling interval is smaller than the preset sampling interval.
摘要翻译：辅助对焦方法适用于具有自动聚焦（AF）过程的图像捕获装置。 AF程序具有预设的采样间隔。辅助聚焦方法包括以下步骤。捕获用于聚焦的图像。计算用于聚焦的图像中的面部块的面部参数。根据面部参数，查找参数对焦转换表以获取聚焦部分。根据聚焦部分和面部采样间隔，执行AF过程以获取目标焦点。面部采样间隔小于预设采样间隔。

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