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21. 发明申请

US20080013565A1 Reverse Polling Algorithm For Shared Resources To Reduce Collisions In A Network 审中-公开
标题翻译：用于共享资源的反向轮询算法以减少网络中的冲突
公开(公告)号：US20080013565A1
公开(公告)日：2008-01-17
申请号：US11457830
申请日：2006-07-17
申请人： Gary W. Batchelor , Brian J. Cagno , Yolanda Colpo
发明人： Gary W. Batchelor , Brian J. Cagno , Yolanda Colpo
IPC分类号： H04L12/413 , H04L12/403
CPC分类号： H04L12/413
摘要： A method for reducing collisions within a plurality of networks, each of the plurality of networks having a plurality of workstations physically communicating over a plurality of shared communication channels, the method comprising: determining if a communication channel is available for transmitting data between the plurality of workstations; transmitting the data between all or part of the plurality of workstations via the communication channel; controlling the transmitted data between the plurality of workstations via a controller; monitoring the transmitted data by using a logic circuit; generating reverse polling of shared resources to reduce the collisions from occurring upon transmitting the data over the communication channel when a determination is made that at least two workstations of the plurality of workstations attempt to access a same shared resource within the plurality of networks; and notifying the controller of the reverse polling of the transmitted data and performing a low frequency time synchronization.
摘要翻译：一种用于减少多个网络中的冲突的方法，所述多个网络中的每一个具有通过多个共享通信信道物理通信的多个工作站，所述方法包括：确定通信信道是否可用于在所述多个网络之间传输数据工作站经由所述通信信道在所述多个工作站的全部或部分之间传送所述数据; 通过控制器控制多个工作站之间的传输数据; 通过使用逻辑电路监视发送的数据; 当确定所述多个工作站中的至少两个工作站尝试访问所述多个网络中的相同共享资源时，生成共享资源的反向轮询以减少在通过所述通信信道发送所述数据时发生的冲突; 并通知控制器对所发送的数据的反向轮询并执行低频时间同步。

22. 发明授权

US08302137B2 Apparatus and method to provide a signal using a communication link 有权
标题翻译：使用通信链路提供信号的装置和方法
公开(公告)号：US08302137B2
公开(公告)日：2012-10-30
申请号：US10675869
申请日：2003-09-29
申请人： Brian J. Cagno , Matthew D. Bomhoff , Gregg S. Lucas , Kenny N. Qiu , Andrew E. Seidel
发明人： Brian J. Cagno , Matthew D. Bomhoff , Gregg S. Lucas , Kenny N. Qiu , Andrew E. Seidel
IPC分类号： H04N7/173 , H04N7/16 , G06F13/00 , G06F13/28
CPC分类号： H04L25/03878
摘要： A method to provide a signal using a communication link. The method disposes a passive transponder on the communication link, where that passive transponder includes a memory. The method reads information relating to the communication link from the memory, and then, based upon that information, adjusts certain characteristics of a signal provided using the communication link.
摘要翻译：一种使用通信链路提供信号的方法。该方法在通信链路上配置无源应答器，其中无源应答器包括存储器。该方法从存储器读取与通信链路相关的信息，然后基于该信息调整使用通信链路提供的信号的某些特性。

23. 发明授权

US08219740B2 Flash sector seeding to reduce program times 有权
标题翻译：闪光扇播种以减少节目时间
公开(公告)号：US08219740B2
公开(公告)日：2012-07-10
申请号：US12146098
申请日：2008-06-25
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Kenny N. Qiu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.
摘要翻译：非易失性闪速存储器包括多个非易失性存储器，其中第一非易失性存储器与所有非易失性存储器被预编程（擦除），并且至少第二非易失性存储器被预编程有种子值，利用减少的编程时间少于六个零。当写入（编程）数据字节时，存储器系统在一个或多个种子表中查找数据字节，以确定存储器系统可以以减少的编程时间写入数据字节的非易失性存储器的一部分。然后，存储器系统将数据字节的位置记录在地址转换表中，以便可以访问数据字节。

24. 发明授权

US08201020B2 Method apparatus and system for a redundant and fault tolerant solid state disk 有权
标题翻译：用于冗余和容错固态盘的方法装置和系统
公开(公告)号：US08201020B2
公开(公告)日：2012-06-12
申请号：US12617023
申请日：2009-11-12
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Andrew D. Walls
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas , Andrew D. Walls
IPC分类号： G06F11/07
CPC分类号： G06F11/2094 , G06F11/2089 , G06F11/2092 , G06F11/2097
摘要： A redundant and fault tolerant solid state disk (SSD) includes a determination module configured to identify a first solid state disk controller (SSDC) configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.
摘要翻译：冗余和容错固态盘（SSD）包括确定模块，其被配置为识别被配置为连接到闪存阵列的第一固态盘控制器（SSDC）和被配置为连接到闪存阵列的第二SSDC。捕获模块被配置为从双端口连接器的端口捕获由第一SSDC接收的I / O请求的副本，和/或从第二SSDC的端口捕获由第二SSDC接收的I / O请求的副本双端口连接器，并从I / O请求中识别写入I / O请求。检测模块被配置为检测第一SSDC中的故障。管理模块被配置为管理由第一SSDC和第二SSDC对闪存阵列的访问。错误恢复和故障切换模块被配置为自动将工作从第一SSDC重新分配给第二SSDC。

25. 发明申请

US20100011261A1 Verifying Data Integrity of a Non-Volatile Memory System during Data Caching Process 有权
标题翻译：在数据缓存过程中验证非易失性存储器系统的数据完整性
公开(公告)号：US20100011261A1
公开(公告)日：2010-01-14
申请号：US12169273
申请日：2008-07-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1064 , G11C29/56 , G11C2029/0407
摘要： To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
摘要翻译：为了确保非易失性闪存的完整性，控制器使用背景测试模式对非易失性存储器进行编程，并在上电自检（POST）操作期间验证非易失性存储器。结合验证非易失性存储器，控制器可以定期地将诊断和状态报告给存储控制器。作为存储控制器上电程序的一部分，存储控制器通过由存储控制器监视的I2C寄存器向控制器发出POST命令。存储控制器可以确定非易失性闪存在没有任何缺陷的情况下起作用，并且控制器可以从非易失性闪存移除电力以扩展其可靠性。定期地，在后台，控制器可以运行诊断例程来检测与易失性存储器和控制器本身相关联的任何故障。

26. 发明申请

US20090323452A1 Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition 失效
标题翻译：双模存储器系统，用于在存储器备份转换期间降低电源需求
公开(公告)号：US20090323452A1
公开(公告)日：2009-12-31
申请号：US12145969
申请日：2008-06-25
申请人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Gregg S. Lucas
IPC分类号： G11C5/14
CPC分类号： G11C5/141
摘要： A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.
摘要翻译：存储器系统的控制器被配置为在存储器备份转换期间减少功率需求。当转换到备份模式时，存储系统控制器执行许多省电技术。控制器可以改变易失性存储器系统中的多个配置设置，例如降低输出驱动器强度，增加差分阻抗，增加片上端接，禁用接收器输入电路以及断开终端电压网络。控制器还可以向存储控制器系统断言硬复位以显着地减少负载，并允许电压调节器持续更长时间地向存储器系统供电。

27. 发明申请

US20090235130A1 TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM 审中-公开
标题翻译：高速SAS网络在制造测试系统中的测试模式自定义
公开(公告)号：US20090235130A1
公开(公告)日：2009-09-17
申请号：US12048766
申请日：2008-03-14
申请人： Brian J. Cagno , Gregg S. Lucas , Thomas S. Truman
发明人： Brian J. Cagno , Gregg S. Lucas , Thomas S. Truman
IPC分类号： H04B17/00 , G06F11/00
CPC分类号： G06F11/24 , G01R31/31716 , G01R31/3183 , G01R31/318378
摘要： A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface.
摘要翻译：一种用于测试高速串行接口的方法，包括：生成被配置为将8bit / 10bit编码方案违反到扩展器中的定制压力测试模式，所述定制压力测试模式被配置为强调高速串行接口超出边缘限制导致较少的测试以强制高速串行接口内的错误; 从高速串行接口的第一串行器/解串器装置的发送端口发送定制的压力测试模式; 以及监视第二串行器/解串器设备的接收端口以检测高速串行接口内的错误。

28. 发明申请

US20080304489A1 APPARATUS AND METHOD TO SET THE SIGNALING RATE OF A NETWORK DISPOSED WITHIN AN INFORMATION STORAGE AND RETRIEVAL SYSTEM 失效
标题翻译：设置信息存储和检索系统中网络信令速率的设备和方法
公开(公告)号：US20080304489A1
公开(公告)日：2008-12-11
申请号：US12196155
申请日：2008-08-21
申请人： MATTHEW D. BOMHOFF , BRIAN J. CAGNO , JOHN C. ELLIOTT , CARL E. JONES , ROBERT A. KUBO , GREGG S. LUCAS , KATHERINE S. TYLDESLEY
发明人： MATTHEW D. BOMHOFF , BRIAN J. CAGNO , JOHN C. ELLIOTT , CARL E. JONES , ROBERT A. KUBO , GREGG S. LUCAS , KATHERINE S. TYLDESLEY
IPC分类号： H04L12/56
CPC分类号： H04L41/0896
摘要： A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.
摘要翻译：公开了一种设置网络速度的方法。该方法提供与系统控制器和多个交换机域互连的网络，其中这些多个交换机域中的每一个包括一个或多个信息存储设备和交换机域控制器，并且由多个交换机域中的每一个设置信令该交换机域的速率。该方法由系统控制器对该交换机域的信令速率的多个交换机域中的每一个进行带内查询，并且为该交换机域的信令速率提供多个交换域中的每一个的带内带内。该方法由系统控制器向系统控制器提供指定第一网络速度的第一速度选择命令，并且由多个交换机域中的每一个将该交换机域的信令速率复位到第一网络速度。

29. 发明授权

US07287708B2 Cooling system control with clustered management services 失效
标题翻译：具有集群管理服务的冷却系统控制
公开(公告)号：US07287708B2
公开(公告)日：2007-10-30
申请号：US10988370
申请日：2004-11-12
申请人： Gregg S Lucas , Robert A Kubo , Brian J Cagno , Matthew D Bomhoff
发明人： Gregg S Lucas , Robert A Kubo , Brian J Cagno , Matthew D Bomhoff
IPC分类号： F24F7/00 , F25D23/12 , H05K7/20
CPC分类号： H05K7/20209 , F25B49/005 , G06F1/206 , G06F11/20 , G06F11/2033
摘要： A data processing unit including a first active cooling device configured to respond to a first control signal and a second active cooling device configured to respond to a second control signal. The control signals may be any type of control signal suitable to control the operation of the first and second active cooling devices. The data processing unit also includes a first control function selectively capable of providing the first control signal and/or the second control signal, and a second control function selectively capable of providing the first control signal and/or the second control signal. Logic associated with the first and second control functions is included to determine which of the control functions will provide which control signal at a specific time. Logic and/or switching or isolation apparatus is also included to prevent both the first and second control functions from attempting to provide one of the control signals simultaneously.
摘要翻译：一种数据处理单元，包括被配置为响应于第一控制信号的第一主动冷却装置和被配置为响应于第二控制信号的第二主动冷却装置。控制信号可以是适于控制第一和第二主动冷却装置的操作的任何类型的控制信号。数据处理单元还包括选择性地能够提供第一控制信号和/或第二控制信号的第一控制功能，以及选择性地能够提供第一控制信号和/或第二控制信号的第二控制功能。包括与第一和第二控制功能相关联的逻辑以确定哪个控制功能将在特定时间提供哪个控制信号。还包括逻辑和/或切换或隔离装置以防止第一和第二控制功能同时尝试提供一个控制信号。

30. 发明授权

US06809675B1 Redundant analog to digital state machine employed to multiple states on a single line 失效
标题翻译：冗余的模拟数字状态机用于单线上的多个状态
公开(公告)号：US06809675B1
公开(公告)日：2004-10-26
申请号：US10795169
申请日：2004-03-05
申请人： Matthew D. Bomhoff , Brian J. Cagno , Gregg S. Lucas , Andrew E. Seidel
发明人： Matthew D. Bomhoff , Brian J. Cagno , Gregg S. Lucas , Andrew E. Seidel
IPC分类号： H03M112
CPC分类号： H03M1/50
摘要： A state machine is used to remove residual electric charge from a sense line and to sample the voltage of the sense line at multiple pre-determined times to determine the presence of a terminating capacitor and its value. Various values of capacitors identify discrete conditions. These discrete conditions may identify different types of plug-in cards or models of plug-in cards within a group type.
摘要翻译：状态机用于从感测线路去除残余电荷，并在多个预定时间对感测线路的电压进行采样，以确定终端电容器的存在及其值。电容的各种值识别离散条件。这些离散条件可以识别不同类型的插件卡或组内类型的插件卡型号。

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