专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06495863B2 Semiconductor device having diode for input protection circuit of MOS structure device 失效
标题翻译：具有用于MOS结构器件的输入保护电路的二极管的半导体器件
公开(公告)号：US06495863B2
公开(公告)日：2002-12-17
申请号：US09883201
申请日：2001-06-19
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L2974
CPC分类号： H01L29/66106 , H01L24/05 , H01L27/0255 , H01L29/7808 , H01L29/866 , H01L2224/45124 , H01L2924/00014 , H01L2924/12035 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/48
摘要： An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.
摘要翻译：设置在用于布置齐纳二极管的区域上的绝缘体膜具有多个凹槽部分，其连续地布置在形成二极管的每个半导体区域的延伸方向D1上。每个沟槽部分在每个半导体区域的宽度方向D2上延伸，并且具有深度T3。每个半导体区域布置在绝缘膜的上表面上。因此，每个半导体区域具有沿着延伸方向D1布置的多个不规则形状，并且齐纳二极管不仅在横向方向D1上而且在垂直方向D3上具有周长，使得pn结面积在齐纳二极管中增加。因此，为了改善二极管的栅极绝缘膜保护功能，降低了输入保护齐纳二极管的寄生电阻。

22. 发明授权

US08809969B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08809969B2
公开(公告)日：2014-08-19
申请号：US12650957
申请日：2009-12-31
申请人： Yoichiro Tarui , Atsushi Narazaki , Ryoichi Fujii
发明人： Yoichiro Tarui , Atsushi Narazaki , Ryoichi Fujii
IPC分类号： H01L29/76
CPC分类号： H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/1608 , H01L29/408 , H01L29/7811 , H01L29/8611 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.
摘要翻译：使用一个或多个保护环的半导体器件包括围绕pn结区域的p型保护环区域，覆盖p型保护环区域的绝缘膜，与p型保护环区域电连接的一个或多个导电膜通过在绝缘膜中形成的一个或多个接触孔，以及覆盖绝缘膜和导电膜的半绝缘膜。因此，即使异物等附着在导电膜的表面，也能够确保期望的击穿电压特性。

23. 发明授权

US08593167B2 Semiconductor device test method and apparatus, and semiconductor device 有权
标题翻译：半导体器件测试方法和装置以及半导体器件
公开(公告)号：US08593167B2
公开(公告)日：2013-11-26
申请号：US13042600
申请日：2011-03-08
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/026 , G01R31/2853 , H01L2924/0002 , H01L2924/00
摘要： A method of testing a semiconductor device includes a conductive foreign matter test step of measuring the resistance value between the first and second conductive patterns to determine whether conductive foreign matter is present between the first and second conductive patterns, a first open circuit test step of measuring the resistance value between two points on the first conductive pattern to determine whether there is an open circuit in the first conductive pattern, and a second open circuit test step of measuring the resistance value between two points on the second conductive pattern to determine whether there is an open circuit in the second conductive pattern. The measurement of the resistance value in each of the test steps is accomplished by pressing probes vertically against the first conductive pattern or the second conductive pattern or both.
摘要翻译：一种测试半导体器件的方法包括：导电异物测试步骤，测量第一和第二导电图案之间的电阻值，以确定导电异物是否存在于第一和第二导电图案之间;第一开路测试步骤，测量确定第一导电图案中的两点之间的电阻值，以确定第一导电图案中是否存在开路;以及第二开路测试步骤，测量第二导电图案上的两个点之间的电阻值，以确定是否存在第二导电图案中的开路。每个测试步骤中的电阻值的测量通过将探针垂直地压靠在第一导电图案或第二导电图案上或两者来实现。

24. 发明授权

US08435417B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435417B2
公开(公告)日：2013-05-07
申请号：US12827259
申请日：2010-06-30
申请人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
发明人： Kazunari Nakata , Kaoru Motonami , Atsushi Narazaki , Ayumu Onoyama , Shigeto Honda , Ryoichi Fujii , Tomoya Hirata
IPC分类号： B44C1/22
CPC分类号： H01L21/3083 , H01L21/304 , H01L21/6835 , H01L21/6836 , H01L2221/68327 , H01L2221/6834 , H01L2924/0002 , H01L2924/30105 , H01L2924/00
摘要： A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.
摘要翻译：在半导体衬底的前表面上形成有从外周端向内侧具有预定宽度且沿外周端部延伸的钝化膜。通过研磨半导体衬底的外周端部形成与前表面和后表面正交的外周端面。通过研磨后表面将半导体衬底的厚度减小到预定厚度。通过将混合酸排放到后表面上同时使后表面朝上的半导体衬底旋转来蚀刻地面后表面，以除去断裂层。由此，能够抑制半导体基板的切削或破裂。

25. 发明申请

US20110220914A1 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20110220914A1
公开(公告)日：2011-09-15
申请号：US12961905
申请日：2010-12-07
申请人： Ryoichi Fujii , Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Ryoichi Fujii , Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/66 , H01L21/302
CPC分类号： H01L29/063 , H01L29/0615 , H01L29/0661 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.
摘要翻译：根据本发明的制造功率半导体器件的方法包括以下步骤：（a）在半导体衬底上形成氮化硅膜; （b）在步骤（a）之后，沿着半导体衬底6的周边部分形成环形沟槽; （c）在所述沟槽的内表面上形成第一氧化硅膜; （d）在步骤（c）之后，在半导体衬底的整个表面上形成第二氧化硅膜以埋置沟槽; （e）通过使用氮化硅膜作为塞子来平坦化第二氧化硅膜; 和（f）在除去氮化硅膜的区域中形成第三氧化硅膜。

26. 发明申请

US20070001265A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070001265A1
公开(公告)日：2007-01-04
申请号：US11276668
申请日：2006-03-09
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L27/082 , H01L29/70 , H01L27/102 , H01L31/11
CPC分类号： H01L23/482 , H01L23/4824 , H01L23/49562 , H01L24/34 , H01L24/37 , H01L24/73 , H01L2224/37147 , H01L2224/37599 , H01L2224/45124 , H01L2224/48463 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： A semiconductor device has a structure capable of connecting a lead terminal directly to an electrode on a front surface thereof. The semiconductor device includes a first main electrode provided on the front surface, a second main electrode provided on a back surface, and a metal film provided so as to cover at least a portion of a surface of the first main electrode and for soldering the lead terminal thereto. Here, the metal film includes a plurality of opening portions through which the surface of the first main electrode is exposed.
摘要翻译：半导体器件具有能够将引线端子直接连接到其表面上的电极的结构。半导体器件包括设置在前表面的第一主电极，设置在背面上的第二主电极和设置成覆盖第一主电极表面的至少一部分并用于焊接引线的金属膜终端。这里，金属膜包括第一主电极的表面露出的多个开口部。

27. 发明授权

US07045831B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07045831B2
公开(公告)日：2006-05-16
申请号：US10918355
申请日：2004-08-16
申请人： Atsushi Narazaki
发明人： Atsushi Narazaki
IPC分类号： H01L29/73 , H01L29/74 , H01L31/111 , H01L27/082 , H01L27/102
CPC分类号： H01L24/05 , H01L23/4827 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/48 , H01L2224/04026 , H01L2224/04042 , H01L2224/05 , H01L2224/05644 , H01L2224/05655 , H01L2224/32245 , H01L2224/45124 , H01L2224/4847 , H01L2224/48491 , H01L2224/48699 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device of the present invention comprises a semiconductor chip, metal layers formed on a first main surface of the semiconductor chip, a first conductive layer layered on a second main surface of the semiconductor chip, consisting of a plurality of conductive films, a second conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip and a third conductive layer layered on the metal layer, having a layered structure consisting of a plurality of conductive films formed in the same order as in the first conductive layer as viewed from the semiconductor chip. The plurality of conductive films comprise a nickel film and a low contact resistance conductive film having contact resistance with the semiconductor chip which is lower than that of the nickel film. The low contact resistance conductive film and the nickel film are formed in this order from the semiconductor chip. With such a structure, a semiconductor device ensuring simplification of its manufacturing process can be provided.
摘要翻译：本发明的半导体器件包括半导体芯片，形成在半导体芯片的第一主表面上的金属层，层叠在半导体芯片的第二主表面上的第一导电层，由多个导电膜构成，第二导电层导电层，层叠在金属层上，具有由从半导体芯片观察的与第一导电层相同的数量形成的多个导电膜和层叠在金属层上的第三导电层构成的层叠结构，由从半导体芯片观察的与第一导电层中的顺序相同的多个导电膜构成的结构。多个导电膜包括与半导体芯片的接触电阻低于镍膜的接触电阻的镍膜和低接触电阻导电膜。低接触电阻导电膜和镍膜从半导体芯片依次形成。通过这样的结构，可以提供确保简化其制造工艺的半导体器件。

28. 发明授权

US06933576B2 Semiconductor device including a predetermined film formed at a border between dielectric films 失效
标题翻译：半导体器件包括在电介质膜之间的边界处形成的预定膜
公开(公告)号：US06933576B2
公开(公告)日：2005-08-23
申请号：US10681303
申请日：2003-10-09
申请人： Katsumi Uryuu , Atsushi Narazaki
发明人： Katsumi Uryuu , Atsushi Narazaki
IPC分类号： H01L29/78 , H01L21/335 , H01L29/423 , H01L21/8238 , H01L29/788
CPC分类号： H01L29/42368 , H01L29/7802
摘要： A semiconductor device includes a silicon oxide film (2) formed in a predetermined region on a single crystalline silicon substrate (1) and a gate dielectric film (3) as a thermal oxide film formed by performing thermal oxidation on the surface of the substrate (1) in a region adjacent to the silicon oxide film (2). A polycrystalline silicon (5) (or amorphous silicon) having an oxidized surface is formed on the border between the silicon oxide film (2) and gate dielectric film (3).
摘要翻译：半导体器件包括形成在单晶硅衬底（1）上的预定区域中的氧化硅膜（2）和作为通过在衬底的表面上进行热氧化形成的热氧化膜的栅极电介质膜（3） 1）在与氧化硅膜（2）相邻的区域中。在氧化硅膜（2）和栅极电介质膜（3）之间的边界上形成具有氧化表面的多晶硅（5）（或非晶硅）。

29. 发明授权

US09431479B2 High breakdown voltage semiconductor device having a resurf layer 有权
标题翻译：具有复层的高耐压电压半导体器件
公开(公告)号：US09431479B2
公开(公告)日：2016-08-30
申请号：US12845176
申请日：2010-07-28
申请人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/06 , H01L29/40 , H01L29/66 , H01L29/861 , H01L29/16 , H01L29/20 , H01L29/78
CPC分类号： H01L29/0615 , H01L29/063 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/66128 , H01L29/7811 , H01L29/8611
摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.
摘要翻译：在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。此外，在凹部上方的绝缘膜上形成场板电极。

30. 发明授权

US08742474B2 Power semiconductor device having an active region and an electric field reduction region 有权
标题翻译：功率半导体器件具有有源区和电场减少区
公开(公告)号：US08742474B2
公开(公告)日：2014-06-03
申请号：US11937725
申请日：2007-11-09
申请人： Yoshiaki Hisamoto , Atsushi Narazaki , Hitoshi Uemura
发明人： Yoshiaki Hisamoto , Atsushi Narazaki , Hitoshi Uemura
IPC分类号： H01L29/66
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/402
摘要： A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.
摘要翻译：本发明的功率半导体器件具有有源区和电场还原区，包括：第一导电型的发射极区; 与发射极区域接触的第二导电类型的基极区域; 所述第一导电类型的电强度提供区域与所述基极区域接触; 与所述电强度提供区域接触的所述第二导电类型的集电极区域; 以及与集电极区域接触的集电极; 其特征在于，所述集电极区域配置在各自含有所述第二导电型掺杂剂的有源区域和电场还原区域上，并且设置在所述电场还原区域上的所述集电极区域包括具有较低密度的载流子的区域，导电类型比设置在有源区上的集电极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式