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21. 发明公开

EP0105122A2 Processes for making ferrite powder and ferrite blocks 失效
标题翻译： Verfahren zur Herstellung von Ferritpulver undFerritblöcken。
公开(公告)号：EP0105122A2
公开(公告)日：1984-04-11
申请号：EP83107606.2
申请日：1983-08-02
申请人： International Business Machines Corporation
发明人： Rigby, Eugene Bertrand
IPC分类号： C01G49/00 , C01G53/00 , C04B35/26 , C04B35/30
CPC分类号： C01G49/0072 , C01G49/0018 , C01G49/0036 , C01G49/0063 , C01G49/009 , C01G53/00 , C01G53/006 , C01P2002/32 , C04B35/26 , C04B35/265
摘要： Fine ferrite powder is produced by adding an ammonium oxalate solution to a solution containing ferrous ions and divalent metal ions to co-precipitate oxalates. After separating, washing and drying the co-precipitated particles, they are calcined for several hours at a relatively low temperature (eg 200°C) before completing the calcination at a higher temperature (eg 800°C). The particles are then vibro-energy or ball milled and dried.
Dense ferrite blocks can be made from the ferrite powder. by pressing the powder into a mold, sintering the molded ferrite and then isostatically pressure compacting it at a temperature of 1200°C and at a pressure of 2.00 x 10 8 Pascals. Dense nickel-zinc ferrite blocks produced in this manner are particularly suitable for the manufacture of magnetic transducer heads.
摘要翻译：通过向含有亚铁离子和二价金属离子的溶液中加入草酸铵溶液共沉淀草酸盐来制备细铁氧体粉末。在分离，洗涤和干燥共沉淀颗粒之后，在较高温度（例如800℃）下完成煅烧之前，将它们在相对低的温度（例如200℃）下煅烧数小时。然后将颗粒振动能量或球磨并干燥。高密度铁氧体块可以由铁氧体粉末制成，通过将粉末压入模具中，烧结成型的铁素体，然后在1200℃的温度和2.00× 10 8帕斯卡。以这种方式生产的密集镍锌铁氧体块特别适用于制造磁性换能器头。

22. 发明公开

EP0097767A2 A semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：EP0097767A2
公开(公告)日：1984-01-11
申请号：EP83102549.9
申请日：1983-03-15
申请人： International Business Machines Corporation
发明人： Dumke, William Paul , Woodall, Jerry MacPherson
IPC分类号： H01L31/10 , H01L29/72
CPC分类号： H01L31/1844 , H01L29/7371 , H01L31/1105 , Y02E10/544
摘要： A semiconductor processor for signals such as are conveyed by fibre optics wherein the processor structure accommodates lattice mismatch and minimizes the effect of misfit dislocations. The structure permits using materials having favorable absorption properties at the 1 micrometer wavelength of optical signals. A binary semiconductor is employed with graded regions produced by adding a different third ingredient in two places so that a wide band optically transparent emitter with a graded base and graded collector are provided. The ingredients impart a strong absorption in the optical signal wavelength together with superior semiconductor carrier transit time. A structure for a silicon and germanium oxide based optical signal fibre uses a GaAlAs emitter, a base that is graded to Ga 25 In 75 As at the collector and then back to GaAs at the substrate.
摘要翻译：用于诸如由光纤传送的信号的半导体处理器，其中处理器结构适应晶格失配并最小化失配位错的效应。该结构允许使用在光学信号的1微米波长处具有良好吸收特性的材料。采用二元半导体，通过在两个位置添加不同的第三成分而产生渐变区域，从而提供具有渐变基底和渐变收集器的宽带光学透明发射体。这些成分赋予光信号波长强大的吸收以及优异的半导体载流子传播时间。基于硅和氧化锗的光学信号光纤的结构使用GaAlAs发射极，基极在集电极处分级为Ga25In75As，然后在基板处返回到GaAs。

23. 发明公开

EP0085761A1 A positive resist composition 失效
标题翻译：正光致抗蚀剂组成。
公开(公告)号：EP0085761A1
公开(公告)日：1983-08-17
申请号：EP82110822.2
申请日：1982-11-23
申请人： International Business Machines Corporation
发明人： Clecak, Nicholas Jeffries , McKean, Dennis Richard , Miller, Robert Dennis , Tompkins, Terry Cady , Twieg, Robert James , Willson, Carlton Grant
IPC分类号： G03F7/08
CPC分类号： G03F7/022
摘要： Positive resists are formed from a soluble phenolic resin and a sensitizer which is a diester of a 1-oxo-2-diazonaphthalene sulfonic acid and of an unsymmetrical primary or secondary aliphatic diol which is a mixture of geometric and diastereoisomers.

24. 发明公开

EP0082331A2 Subsurface avalanche breakdown Zener diode 失效
标题翻译：齐纳二极管与体积雪崩击穿。
公开(公告)号：EP0082331A2
公开(公告)日：1983-06-29
申请号：EP82110812.3
申请日：1982-11-23
申请人： International Business Machines Corporation
发明人： Muggli, Raymond Allen
IPC分类号： H01L29/90
CPC分类号： H01L29/866
摘要： This zener diode is fabricated by a conventional CMOS device fabricating process whereby an entire electronic circuit can be laid down in one overall process. A semiconductor substrate (10) of one conductivity type has an elongate region (12) of semiconductor material of the opposite conductivity type diffused to a predetermined depth to form a well, centrally of which a region (18) of enhanced conductivity material of the opposite conductivity type is diffused to a prearranged depth less than the predetermined depth. Semiconductor material of the one conductivity type is diffused into a pair of elongate regions (14, 16) spaced apart from, and with one on each side of, the first elongate region (12) while at the same time a quantity of the same material is diffused into the substrate between the pair of regions (14, 16) and over the central region (18) and doped more heavily than the substrate material to convert the upper part of the central region (18) and the well (12) to the opposite conductivity type for a substantial depth into the well whereby a P + N + junction is formed completely beneath the surface of the substrate. One contact (22) for the zener diode is made to the well region (12) outside the conductivity type converted part of the well. The other contact (24) is made to one (16) of the pair of regions (14.16).

25. 发明公开

EP0081626A2 Dual electron injector structure and semiconductor memory device including a dual electron injector structure 失效
标题翻译： Doppel-Elektroneninjektionsstruktur und Halbleiterspeicheranordnung mit Doppel-Elektroneninjektionsstruktur。
公开(公告)号：EP0081626A2
公开(公告)日：1983-06-22
申请号：EP82105481.4
申请日：1982-06-23
申请人： International Business Machines Corporation
发明人： Dimaria, Donelli Joseph , Dong, David Wah
IPC分类号： G11C11/34 , G11C17/00 , H01L29/60
CPC分类号： H01L29/7882
摘要： A DEIS (Dual Electron Injector Structure) EAROM (Electrically Alterable Read Only Memory) device has a silicon-rich, silicon dioxide region 5 between the dual injector regions (1, 3). The region (5) has an excess of silicon therein which is less than the excess of silicon in the injector regions (1, 3). The device differs from known DEIS EAROM devices in that the insulator layer between the injectors is rendered conductive to a desired degree by causing a compound insulator like SiO 2 to be off-stoichiometry during deposition so that the resulting insulator becomes silicon rich. Alternatively, the insulator may be deposited together with material which renders the insulator conductive or a metallic specie may be added to the insulator by diffusion or ion Implantation after the insulator is formed. The resulting slightly conductive insulator provides a means for draining off trapped charge in the insulator resulting in a device of such improved cyclibility that the DEIS EAROM can be used as a Non-Volatile Random Access Memory (NVRAM) capable of from 10 8 to greater than 10 10 cycles before threshold collapse occurs.
The conductive insulator is designed so that it is conductive only at high electric fields encountered during writing and erasing and highly blocking at low fields encountered during reading or storage operations.
摘要翻译： DEIS（双电子注入器结构）EAROM（电可更改只读存储器）器件在双注入器区域（1,3）之间具有富含硅的二氧化硅区域5。区域（5）中的硅含量过多，其小于喷射器区域（1,3）中硅的过量。该装置与已知的DEIS EAROM装置的不同之处在于，通过在沉积期间使诸如SiO 2的复合绝缘体离开化学计量，使得所得绝缘体变成富硅，使注入器之间的绝缘体层达到所需的程度。或者，绝缘体可以与形成绝缘体的材料一起沉积在导体上，或者在形成绝缘体之后通过扩散或离子注入将金属物质加入到绝缘体中。所得到的稍微导电的绝缘体提供了用于排出绝缘体中的俘获电荷的装置，导致具有这种改进的可循环性的装置，使得DEIS EAROM可以用作能够从10 8到...的非易失性随机存取存储器（NVRAM）阈值崩溃之前大于10 <1> 0个周期。导电绝缘体被设计成仅在写入和擦除期间遇到的高电场和在读取或存储操作期间遇到的低场强度高度阻塞时才导电。

26. 发明公开

EP0077445A2 A method of forming an electronic circuit structure 失效
标题翻译： Verfahren zur Herstellung einer elektronischen Schaltkreisstruktur。
公开(公告)号：EP0077445A2
公开(公告)日：1983-04-27
申请号：EP82107379.8
申请日：1982-08-13
申请人： International Business Machines Corporation
发明人： Broers, Alec Nigel , Laibowitz, Robert Benjamin
IPC分类号： H01L21/00
CPC分类号： G03F7/70425 , G03F7/0957 , G03F7/2022 , H01L21/0277 , H05K3/0082 , H05K3/048 , H05K3/064 , H05K2201/0108 , H05K2203/1572
摘要： This invention discloses double sided lithography for fabricating ultra-small multilayer microcircuit structures without need for any intermediate realignment and without need for any intermediate layer deposition involving reestablishment of surface planarity. Microcircuit patterns (96, 98) are defined on opposite sides of a thin substrate (50) by an exposure tool without intermediate removal of the substrate (50) from the exposure tool, the microcircuit pattern (96) on one side being defined by incident patterning radiation and the microcircuit pattern (98) on the other side being defined by patterning radiation which has passed through the thin substrate.
摘要翻译：本发明公开了用于制造超小型多层微型电路结构的双面光刻，而不需要任何中间重新对准，并且不需要涉及重新建立表面平面度的任何中间层沉积。微电路图案（96,98）通过曝光工具限定在薄基板（50）的相对侧上，而不会从曝光工具中间移除基板（50），一侧的微电路图案（96）由入射图案化辐射和另一侧的微电路图案（98）通过图案化已经穿过薄衬底的辐射来限定。

27. 发明公开

EP0068064A1 Semiconductor circuit including a resonant quantum mechanical tunnelling triode device 失效
标题翻译： Halbleiterschaltung mit einer resonance arbeitenden Tunnel-Triode。
公开(公告)号：EP0068064A1
公开(公告)日：1983-01-05
申请号：EP82100162.5
申请日：1982-01-12
申请人： International Business Machines Corporation
发明人： Esaki, Leo
IPC分类号： H01L29/76 , H01L29/205
CPC分类号： B82Y10/00 , H01L29/7606
摘要： A semiconductor circuit includes a triode device (1) wherein majority carrier transport is by quantum mechanical resonant tunnelling through two barriers. The device is constructed of three layers (2, 3, 4) of the same conductivity type monocrystalline semiconductor material. There are identical barriers between the first (2) and second (3) layers and the second (3) and third (4) layers. The layers are doped and biased so that electrons are in all three layers. The width and doping of the second layer (3) are such that it provides a potential well with lower (E,) and higher (E,) quasistationary energy states. The bias voltages applied to the second (3) and third (4) layers cause the higher quasistationary energy state (E 2 ) to be aligned with the Fermi level (E f ) in the first layer (2). The device provides switching speeds of the order of 10- 12 seconds.
摘要翻译：半导体电路包括三极管器件（1），其中多数载流子传输是通过两个屏障的量子力学谐振隧穿。该器件由相同导电型单晶半导体材料的三层（2,3,4）构成。在第一层（2）层和第二层（3）层和第二层（3）层和第三层（4层）之间存在相同的屏障。这些层被掺杂和偏置，使得电子全部为三层。第二层（3）的宽度和掺杂使得它提供具有较低（E1）和更高（E2）准静态能态的势阱。施加到第二层（3）和第三层（4）的偏置电压导致更高的准稳态能态（E2）与第一层（2）中的费米能级（Ef）对准。该设备提供10 < - > 1 <2>秒的开关速度。

28. 发明公开

EP0066042A2 Methods of processing a silicon substrate for the formation of an integrated circuit therein 失效
标题翻译：一种用于治疗用于生产集成电路的由硅制成的基片的方法在所述衬底上。
公开(公告)号：EP0066042A2
公开(公告)日：1982-12-08
申请号：EP82101676.3
申请日：1982-03-04
申请人： International Business Machines Corporation
发明人： Lever, Reginald Frank , Raacke, Karl Heinz
IPC分类号： H01L21/76 , H01L21/306 , H01L21/316
CPC分类号： H01L21/02238 , H01L21/02252 , H01L21/3065 , H01L21/3085 , H01L21/31612
摘要： A region of a silicon substrate is simultaneously etched and a silicon dioxide deposit formed on the sidewalls of the etched region by masking the substrate except in the region to be etched and subjecting the substrate to a plasma in a gas containing a fluorohalogenohydrocarbon and oxygen, the oxygen content being between 40 and 80 percent by volume. Thus, a trench (36) is plasma etched in a region of a silicon substrate (30) not protected by a masking layer (32) and a silicon dioxide deposit (34) is formed on the sidewalls of the trench (36). The fluorohalogenohydrocarbon may be CCl 2 F 2 . Other hydrocarbons containing chlorine or bromine or iodine, as well as fluorine, may also be used.
摘要翻译：硅衬底的区域被同时蚀刻和通过掩蔽基片除了在区域形成在蚀刻区域的侧壁上的二氧化硅沉积物被蚀刻并对该基材至等离子体的气体在含有fluorohalogenohydrocarbon和氧气，所述氧含量为40体积％和80％之间。因此，沟槽（36）是血浆中不通过掩模层（32）和二氧化硅沉积物（34）保护的硅衬底（30）的区域进行蚀刻形成在沟槽（36）的侧壁上。该fluorohalogenohydrocarbon可能是CCl2F2。含氯或溴或碘，以及其它氟烃类，因此可以使用。

29. 发明公开

EP0056453A2 Printhead for electrochromic printing and method of fabricating such printhead 失效
标题翻译：一种用于电致变色印刷的打印头，和用于制造这样的打印头。
公开(公告)号：EP0056453A2
公开(公告)日：1982-07-28
申请号：EP81109764.1
申请日：1981-11-19
申请人： International Business Machines Corporation
发明人： Kendall, Arthur Harry , Mitchell, Joseph William , Sambucetti, Carlos Juan
IPC分类号： B41J3/20
CPC分类号： B41J2/395 , Y10T29/49117
摘要： An electrochromic printhead comprises a housing of insulating material in which there is sealed an array of spaced, precisely positioned, capillary tubes. An active print electrode (34) which defines one dot of an array or matrix of dots is disposed within each of the capillary tubes. At least one reference electrode (36) is disposed in operative relationship to each of the print electrodes so that a voltage may be applied between selected active electrodes and the reference electrode to define a particular printing pattern. Each active electrode may be formed by a conductive coating applied along the interior surface of the capillary tube, or by a cylindrical wire positioned within the capillary tube, or by a conductive filler in the capillary tube.

30. 发明公开

EP0051134A2 Field effect transistor circuit arrangements 失效
标题翻译： Feldeffekttransistor Schaltkreisanordnung。
公开(公告)号：EP0051134A2
公开(公告)日：1982-05-12
申请号：EP81107091.1
申请日：1981-09-09
申请人： International Business Machines Corporation
发明人： Fang, Frank Fu , Sai-Halasz, George Anthony
IPC分类号： H01L29/78 , H01L29/10
CPC分类号： H01L29/105 , H01L29/1033 , H01L29/1083 , H01L29/7722 , H01L29/78657
摘要： A field effect transistor has operating characteristics based on the control and modulation of the punchthrough phenomenon as well as the space charge limited conduction of channel current. The channel region (20) between the source (22) and the drain (24) regions is appropriately doped p-type such that the depletion zones of the n + doped source and drain regions overlap. In the absence of the gate field there is a potential barrier in the overlapped depletion zones high enough to prevent injection of electrons for channel conduction, and low enough to be modulated to below the kT/q barrier height criterion by the gate- and the source-to- drain fields. The actual barrier height potential is determined by the doping and channel length. When a positive voltage is applied to the gate, the gate field will cause the potential in the channel to be reduced much the same way as the external field affects an insulator. In addition to the gate field, the source-drain potential introduces a longitudinal field which also modulates and distorts the barrier. Alternative structures have an insulating substrate or a semiconductor substrate and buried semiconductor layer forming the barrier.
摘要翻译：场效应晶体管具有基于穿通现象的控制和调制以及沟道电流的空间电荷限制传导的操作特性。源极（22）和漏极（24）区域之间的沟道区域（20）被适当地掺杂p型，使得n +掺杂的源极和漏极区域的耗尽区域重叠。在没有栅极场的情况下，在重叠的耗尽区域中存在足够高的阻挡层，以防止电子注入用于沟道传导，并且足够低以便通过栅极和源极被调制到低于kT / q势垒高度标准到排水场。实际势垒高度电位由掺杂和沟道长度决定。当正电压施加到栅极时，栅极场将导致通道中的电位与外部电场影响绝缘体的方式相同。除了栅极场，源极 - 漏极电位引入了纵向场，其也调制和扭曲势垒。替代结构具有绝缘衬底或形成屏障的半导体衬底和掩埋半导体层。

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