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21. 发明专利

AU2002330921A1 Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication 未知
公开(公告)号：AU2002330921A1
公开(公告)日：2003-03-03
申请号：AU2002330921
申请日：2002-07-26
申请人： MATRIX SEMICONDUCTOR INC
发明人： JOHNSON MARK G
IPC分类号： G11C17/16 , G11C7/00 , H01L21/82
摘要： A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

22. 发明专利

AU2002336227A1 Method and apparatus for biasing selected and unselected array lines when writing a memory array 未知
公开(公告)号：AU2002336227A1
公开(公告)日：2002-10-08
申请号：AU2002336227
申请日：2002-03-21
申请人： MATRIX SEMICONDUCTOR INC
发明人： SCHEUERLEIN ROY E
IPC分类号： G11C5/02 , G11C7/06 , G11C7/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/18
摘要： A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.

23. 发明申请

WO2006078505A3 A NON-VOLATILE MEMORY CELL COMPRISING A DIELECTRIC LAYER AND A PHASE CHANGE MATERIAL IN SERIES 审中-公开
标题翻译：包含电介质层和相变材料的非易失性存储元件系列
公开(公告)号：WO2006078505A3
公开(公告)日：2009-06-04
申请号：PCT/US2006000774
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR INC , SCHEUERLEIN ROY E , HERNER S BRAD
发明人： HERNER S BRAD
IPC分类号： G11C17/00 , G11C7/00 , G11C11/39 , G11C17/16 , H01L21/336 , H01L21/82 , H01L27/24 , H01L29/04 , H01L29/73 , H01L45/00
CPC分类号： G11C5/02 , G11C11/39 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C17/16 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： The invention provides for a nonvolatile memory cell comprising a dielectric material (28) in series with a phase change material (30), such as a chalcogenide Phase change is achieved in chalcogenide memories by thermal means Concentrating thermal energy in a relatively small volume assists this phase change By applying high voltage across a dielectric layer, dielectric breakdown occurs, forming a low-resistance rupture region traversing the dielectric layer This rupture region can serve to concentrate thermal energy in a phase-change memory cell In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.
摘要翻译：本发明提供了一种非易失性存储单元，其包括与相变材料（30）串联的介电材料（28），例如硫族化物。通过热方法在硫族化物存储器中实现相变在较小体积中集中热能有助于该相变通过在电介质层上施加高电压，发生电介质击穿，形成穿过电介质层的低电阻断裂区域。该破裂区域可用于将热能聚集在相变存储器单元中。在优选实施例中，可用于单片三维存储器阵列。

24. 发明申请

WO2006073735A1 APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS 审中-公开
标题翻译：使用多级解码器的多级别进行DENSE存储器阵列的分层解码的装置和方法
公开(公告)号：WO2006073735A1
公开(公告)日：2006-07-13
申请号：PCT/US2005/045564
申请日：2005-12-16
申请人： MATRIX SEMICONDUCTOR, INC. , FASOLI, Luca, G. , SO, Kenneth, K.
发明人： FASOLI, Luca, G. , SO, Kenneth, K.
IPC分类号： G11C5/06
CPC分类号： G11C8/10 , G11C16/08 , Y10T29/49002
摘要： A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.
摘要翻译：包括耦合到存储器单元的第一和第二类型的阵列线的存储器阵列包括用于解码地址信息并选择第一类型的一个或多个阵列线的第一分层解码器电路。第一分层解码器电路包括至少两个分层级的多头解码器电路。第一分层解码器电路可以包括用于对多个地址信号输入进行解码并生成多个第一级解码输出的第一级解码器电路，多个第二级多头解码器电路，每个相应的一个耦合到各自的第一级解码输出，每个用于提供相应的多个第二级解码输出，以及多个第三级多头解码器电路，每个解码器电路分别耦合到相应的二级解码输出，每个用于提供一个耦合到存储器阵列的相应的多个第三级解码输出。

25. 发明申请

WO2005057586A3 NAND MEMORY ARRAY INCORPORATING MULTIPLE SERIES SELECTION DEVICES AND METHOD FOR OPERATION OF SAME 审中-公开
标题翻译：并入多个系列选择装置的NAND存储器阵列及其操作方法
公开(公告)号：WO2005057586A3
公开(公告)日：2005-09-09
申请号：PCT/US2004040283
申请日：2004-12-02
申请人： MATRIX SEMICONDUCTOR INC , CHEN EN-HSING , WALKER ANDREW J , SCHEUERLEIN ROY E , NALLAMOTHU SUCHETA , ILKBAHAR ALPER , FASOLI LUCA G , CLEEVES JAMES M
发明人： CHEN EN-HSING , WALKER ANDREW J , SCHEUERLEIN ROY E , NALLAMOTHU SUCHETA , ILKBAHAR ALPER , FASOLI LUCA G , CLEEVES JAMES M
IPC分类号： G11C8/08 , G11C16/04 , G11C16/08 , G11C16/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/3418 , G11C16/3427
摘要： An exemplary NAND string memory array (300) provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple series select devices at one or both ends of each NAND string reduce leakage through such select devices, for both unselected and selected NAND strings. An exemplary memory array may include series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells (400) formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列（300）提供用于半选择的存储器单元通道的电容性升压以减少半选择单元的编程干扰效应。为了降低升压电平的漏电流劣化的影响，在NAND串的一端或两端的多个串联选择器件减少了对于未选择和选择的NAND串的这些选择器件的泄漏。示例性存储器阵列可以包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面（400）。

26. 发明申请

WO2005057586A2 NAND MEMORY ARRAY INCORPORATING MULTIPLE SERIES SELECTION DEVICES AND METHOD FOR OPERATION OF SAME 审中-公开
标题翻译：并入多个系列选择装置的NAND存储器阵列及其操作方法
公开(公告)号：WO2005057586A2
公开(公告)日：2005-06-23
申请号：PCT/US2004/040283
申请日：2004-12-02
申请人： MATRIX SEMICONDUCTOR, INC. , CHEN, En-Hsing , WALKER, Andrew J. , SCHEUERLEIN, Roy E. , NALLAMOTHU, Sucheta , ILKBAHAR, Alper , FASOLI, Luca G. , CLEEVES, James M.
发明人： CHEN, En-Hsing , WALKER, Andrew J. , SCHEUERLEIN, Roy E. , NALLAMOTHU, Sucheta , ILKBAHAR, Alper , FASOLI, Luca G. , CLEEVES, James M.
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/3418 , G11C16/3427
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple series select devices at one or both ends of each NAND string reduce leakage through such select devices, for both unselected and selected NAND strings. An exemplary memory array may include series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了降低升压电平的漏电流劣化的影响，在NAND串的一端或两端的多个串联选择器件减少了对于未选择和选择的NAND串的这些选择器件的泄漏。示例性存储器阵列可以包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

27. 发明申请

WO2004061851A3 AN IMPROVED METHOD FOR MAKING HIGH-DENSITY NONVOLATILE MEMORY 审中-公开
标题翻译：用于制造高密度非易失性存储器的改进方法
公开(公告)号：WO2004061851A3
公开(公告)日：2005-06-23
申请号：PCT/US0339612
申请日：2003-12-12
申请人： MATRIX SEMICONDUCTOR INC
发明人： HERNER S BRAD , MAHAJANI MAITREYEE , VYVODA MICHAEL A
IPC分类号： G11C20060101 , G11C5/02 , H01L21/00 , H01L21/331 , H01L21/82 , H01L21/8238 , H01L23/48 , H01L27/102 , H01L27/148 , H01L29/94 , H01L31/0392 , H01L31/119
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.
摘要翻译：一种用于制造密度增加的三维单片存储器的改进方法。该方法包括形成优选包含钨的导体，然后填充和平坦化; 在形成半导体元件的导体之上，优选地包括两个二极管部分和反熔丝，然后填充和平坦化; 并在多层故事中继续形成导体和半导体元件。处理步骤的布置和材料的选择降低了每个存储单元的纵横比，提高了间隙填充的可靠性并防止蚀刻底切。

28. 发明申请

WO2004095461A3 REDUNDANT MEMORY STRUCTURE USING BAD BIT POINTERS 审中-公开
标题翻译：使用边缘点的冗余存储器结构
公开(公告)号：WO2004095461A3
公开(公告)日：2005-05-19
申请号：PCT/US2004008117
申请日：2004-03-15
申请人： MATRIX SEMICONDUCTOR INC , SCHEUERLEIN ROY E , JOHNSON MARK G , BOSCH DEREK J , ILKBAHAR ALPER , TRINGALI J JAMES
发明人： SCHEUERLEIN ROY E , JOHNSON MARK G , BOSCH DEREK J , ILKBAHAR ALPER , TRINGALI J JAMES
IPC分类号： G11C7/10 , G11C7/24 , G11C29/00 , G11C29/44 , G11C7/00
CPC分类号： G11C29/76 , G11C7/1006 , G11C7/24 , G11C29/44 , G11C29/4401 , G11C29/78
摘要： The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells (100), and an error is detected in writing data in one of the memory cells (100). In response to the detected error, a pointer (130) is written in a second plurality of memory cells (100), the pointer (130) identifying which memory cell (100) in the first plurality of memory cells (100) contains the error. During a read operation, the data is read from the first plurality of memory cells (100), and the pointer (130) is read from the second plurality of memory cells (100). From the pointer (130), the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：这里描述的优选实施例涉及使用坏比特指针的冗余存储器结构。在一个优选实施例中，数据被写入第一多个存储单元（100）中，并且在存储单元（100）之一中写入数据时检测到错误。响应于检测到的错误，指针（130）被写入第二多个存储单元（100）中，指示器（130）识别第一多个存储单元（100）中的哪个存储单元（100）包含错误。在读取操作期间，从第一多个存储器单元（100）读取数据，并且从第二多个存储器单元（100）读取指针（130）。从指针（130）中，识别包含错误的存储单元，并纠正错误。提供了其它优选实施方案，并且各个优选实施方案可以单独使用或彼此组合使用。

29. 发明申请

WO2004061863A2 PROGRAMMABLE MEMORY ARRAY STRUCTURE INCORPORATING SERIES-CONNECTED TRANSISTOR STRINGS AND METHODS FOR FABRICATION AND OPERATION OF SAME 审中-公开
标题翻译：包含系列连接晶体管的可编程存储器阵列结构及其制造和操作的方法
公开(公告)号：WO2004061863A2
公开(公告)日：2004-07-22
申请号：PCT/US2003/041446
申请日：2003-12-29
申请人： MATRIX SEMICONDUCTOR, INC.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher , WALKER, Andrew J., , CHEN, En-Hsing , NALLAMOTHU, Sucheta , ILKBAHAR, Alper , FASOLI, Luca G., , KOUZNETSOV, Igor
IPC分类号： G11L
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/10 , G11C16/16 , H01L27/11565 , H01L27/1157
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer, preferably connected together by way of vertical stacked vias.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。每个NAND串包括两个块选择装置，用于分别将NAND串的一端耦合到全局位线，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是这样。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线，优选地通过垂直堆叠通孔连接在一起。

30. 发明申请

WO2003017285A1 NONVOLATILE MEMORY ON SOI AND COMPOUND SEMICONDUCTOR SUBSTRATES AND METHODS OF FABRICATION 审中-公开
标题翻译： SOI和化合物半导体衬底上的非易失性存储器和制造方法
公开(公告)号：WO2003017285A1
公开(公告)日：2003-02-27
申请号：PCT/US2002/021318
申请日：2002-08-12
申请人： MATRIX SEMICONDUCTOR, INC. , WALKER, Andrew, J. , JOHNSON, Mark, G. , KNALL, N., Johan , KOUZNETSOV, Igor, G. , PETTI, Christopher, J.
发明人： WALKER, Andrew, J. , JOHNSON, Mark, G. , KNALL, N., Johan , KOUZNETSOV, Igor, G. , PETTI, Christopher, J.
IPC分类号： G11C17/00
CPC分类号： H01L27/11568 , G11C16/0466 , H01L21/822 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11578
摘要： A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit (2), and a substrate (3). The at least one driver circuit (2) is not located in a bulk monocrystalline silicon substrate (7). The at least one driver circuit may be located in a silicon on insulator substrate (3) or in a compound substrate.
摘要翻译：提供非易失性存储器阵列。阵列包括非易失性存储器件阵列，至少一个驱动电路（2）和衬底（3）。至少一个驱动电路（2）不位于大块单晶硅衬底（7）中。至少一个驱动器电路可以位于绝缘体上硅衬底（3）上或复合衬底中。

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