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1. 发明申请

WO2006078505A3 A NON-VOLATILE MEMORY CELL COMPRISING A DIELECTRIC LAYER AND A PHASE CHANGE MATERIAL IN SERIES 审中-公开
标题翻译：包含电介质层和相变材料的非易失性存储元件系列
公开(公告)号：WO2006078505A3
公开(公告)日：2009-06-04
申请号：PCT/US2006000774
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR INC , SCHEUERLEIN ROY E , HERNER S BRAD
发明人： HERNER S BRAD
IPC分类号： G11C17/00 , G11C7/00 , G11C11/39 , G11C17/16 , H01L21/336 , H01L21/82 , H01L27/24 , H01L29/04 , H01L29/73 , H01L45/00
CPC分类号： G11C5/02 , G11C11/39 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C17/16 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： The invention provides for a nonvolatile memory cell comprising a dielectric material (28) in series with a phase change material (30), such as a chalcogenide Phase change is achieved in chalcogenide memories by thermal means Concentrating thermal energy in a relatively small volume assists this phase change By applying high voltage across a dielectric layer, dielectric breakdown occurs, forming a low-resistance rupture region traversing the dielectric layer This rupture region can serve to concentrate thermal energy in a phase-change memory cell In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.
摘要翻译：本发明提供了一种非易失性存储单元，其包括与相变材料（30）串联的介电材料（28），例如硫族化物。通过热方法在硫族化物存储器中实现相变在较小体积中集中热能有助于该相变通过在电介质层上施加高电压，发生电介质击穿，形成穿过电介质层的低电阻断裂区域。该破裂区域可用于将热能聚集在相变存储器单元中。在优选实施例中，可用于单片三维存储器阵列。

2. 发明申请

WO2009099943A2 METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA 审中-公开
标题翻译：形成包含薄层薄膜的光电池的方法
公开(公告)号：WO2009099943A2
公开(公告)日：2009-08-13
申请号：PCT/US2009032647
申请日：2009-01-30
申请人： TWIN CREEKS TECHNOLOGIES INC , SIVARAM SRINIVASAN , AGARWAL ADITYA , HERNER S BRAD , PETTI CHRISTOPHER J
发明人： SIVARAM SRINIVASAN , AGARWAL ADITYA , HERNER S BRAD , PETTI CHRISTOPHER J
IPC分类号： H01L31/042
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.
摘要翻译：通过在诸如半导体晶片的施主体的表面下方注入气体离子形成非常薄的光伏电池。离子注入限定了解理面，随后的步骤在切割平面处从晶片剥离薄层。光伏电池，或光伏电池的基极或发射极的全部或一部分形成在薄片内。在优选实施例中，在切割步骤之前将晶片固定到接收器。电接触可以形成在层的两个表面上，或仅形成在一个表面上。

3. 发明申请

WO2006121837A3 NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL 审中-公开
标题翻译：包含二极管和电阻切换材料的非易失性存储单元
公开(公告)号：WO2006121837A3
公开(公告)日：2007-01-04
申请号：PCT/US2006017376
申请日：2006-05-05
申请人： SANDISK 3D LLC , HERNER S BRAD , KUMAR TANMAY , PETTI CHRISTOPHER J
发明人： HERNER S BRAD , KUMAR TANMAY , PETTI CHRISTOPHER J
IPC分类号： G11C13/02 , G11C16/02 , H01L23/525 , H01L27/102 , H01L27/24
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y . In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.
摘要翻译：在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选地为金属氧化物或氮化物，例如Ni x O y O y，铌，铌，铌，钇，铌，SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB 其中，O x Y y O y，Y x O y，Y O x O x，X x O，O x O，X x O， y，x，x，y，y，x，y，x，y，x， / SUB＆gt; Y＆gt;和＆lt; N＆gt; N＆lt; / SUB＆gt;。在优选实施例中，二极管形成为设置在导体之间的垂直支柱。可以堆叠多个存储器级别以形成单片三维存储器阵列。在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

4. 发明申请

WO2008005412A3 ULTRASHALLOW SEMICONDUCTOR CONTACT BY OUTDIFFUSION FROM A SOLID SOURCE 审中-公开
标题翻译： ULTRASHALLOW SEMICONDUCTOR通过来自固体源的扩散来接触
公开(公告)号：WO2008005412A3
公开(公告)日：2008-05-08
申请号：PCT/US2007015321
申请日：2007-06-29
申请人： SANDISK 3D LLC , HERNER S BRAD , RADIGAN STEVEN J
发明人： HERNER S BRAD , RADIGAN STEVEN J
IPC分类号： H01L21/225 , H01L21/285 , H01L27/102
CPC分类号： H01L27/1021 , H01L21/02425 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/2254
摘要： The surface of a conductive layer such as a conductive nitride, a conductive suicide, a metal, or metal alloy or compound, is exposed to a dopant gas which provides an n-type or p-type dopant. The dopant gas may be included in a plasma. Semiconductor material, such as silicon, germanium, or their alloys, is deposited directly on the surface which has been exposed to the dopant gas. During and subsequent to deposition, dopant atoms diffuse into the deposited semiconductor, forming a thin heavily doped region and making a good ohmic contact between the semiconductor material and the underlying conductive layer.
摘要翻译：诸如导电氮化物，导电硅化物，金属或金属合金或化合物的导电层的表面暴露于提供n型或p型掺杂剂的掺杂剂气体。掺杂剂气体可以包含在等离子体中。诸如硅，锗或它们的合金的半导体材料直接沉积在已经暴露于掺杂剂气体的表面上。在沉积期间和之后，掺杂剂原子扩散到沉积的半导体中，形成薄的重掺杂区并在半导体材料和下面的导电层之间形成良好的欧姆接触。

5. 发明申请

WO2006121924A3 HIGH-DENSITY NONVOLATILE MEMORY ARRAY FABRICATED AT LOW TEMPERATURE COMPRISING SEMICONDUCTOR DIODES 审中-公开
标题翻译：高密度非易失性存储器阵列在包含半导体二极管的低温下制作
公开(公告)号：WO2006121924A3
公开(公告)日：2007-03-01
申请号：PCT/US2006017525
申请日：2006-05-05
申请人： SANDISK 3D LLC , HERNER S BRAD , DUNTON SAMUEL V
发明人： HERNER S BRAD , DUNTON SAMUEL V
IPC分类号： H01L27/06 , H01L27/102
CPC分类号： H01L27/1021 , H01L27/0688
摘要： A memory cell is described suitable for use in a high-density monolithic three dimensional memory array. In preferred embodiments of the memory cell, a semiconductor junction diode formed of germanium or a germanium alloy which can be crystallized at relatively low temperature is formed disposed between conductors. The use of a low-temperature material allows the conductors to be formed of copper or aluminum, both low-resistivity materials that provide adequate current at very small feature size, allowing for a highly dense stacked array.
摘要翻译：描述适合用于高密度单片三维存储器阵列的存储单元。在存储单元的优选实施例中，形成由锗或锗合金形成的可在较低温度下结晶的半导体结二极管，形成在导体之间。使用低温材料允许导体由铜或铝形成，这两种低电阻率材料都以非常小的特征尺寸提供足够的电流，允许高度密集的堆叠阵列。

6. 发明申请

WO2009005700A3 MEMORY CELL THAT EMPLOYS A SELECTIVELY DEPOSITED REVERSIBLE RESISTANCE-SWITCHING ELEMENT AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：内存单元，使用选择性保存的可逆电阻切换元件和形成相同的方法
公开(公告)号：WO2009005700A3
公开(公告)日：2009-02-26
申请号：PCT/US2008007986
申请日：2008-06-27
申请人： SANDISK 3D LLC , SCHRICKER APRIL , HERNER S BRAD , KONEVECKI MICHAEL
发明人： SCHRICKER APRIL , HERNER S BRAD , KONEVECKI MICHAEL
IPC分类号： H01L27/10
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了一种形成存储器单元的方法，其包括（1）在衬底上方形成第一导体; （2）在第一导体上方形成二极管; （3）使用选择性沉积工艺在第一导体上方形成可逆电阻切换元件; （4）在二极管和可逆电阻切换元件上方形成第二导体。许多其他方面提供。

7. 发明申请

WO2009045920A3 VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有较低编程电压的基于垂直二极管的存储器单元及其形成方法
公开(公告)号：WO2009045920A3
公开(公告)日：2009-06-11
申请号：PCT/US2008077960
申请日：2008-09-26
申请人： SANDISK 3D LLC , HERNER S BRAD , KUMAR TANMAY
发明人： HERNER S BRAD , KUMAR TANMAY
IPC分类号： H01L27/115
CPC分类号： H01L27/1021 , G11C17/16 , H01L23/5252 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a suicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of suicide, silicide- germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided.
摘要翻译：在第一方面，提供了一种用于形成非易失性存储器单元的方法。该方法包括（1）形成包括（a）第一金属层的金属 - 绝缘体 - 金属（MIM）反熔丝堆叠; （b）在第一金属层上方形成的二氧化硅，氮氧化物或氮化硅反熔丝层; 和（c）在反熔丝层上方形成的第二金属层。该方法还包括（2）在MIM堆叠之上形成连续的p-i-n二极管，连续的p-i-n二极管包括沉积的半导体材料; （3）形成与沉积的半导体材料接触的硅化物，硅化物 - 锗化物或锗化物层; （4）使沉积的半导体材料与硅化物，硅化物 - 锗化物或锗化物层接触结晶。存储器单元包括连续的p-i-n二极管和MIM堆栈。其他方面提供。

8. 发明申请

WO2009002476A3 NONVOLATILE MEMORY DEVICE CONTAINING A CARBON- OR NITROGEN-DOPED DIODE AND METHODS OF MAKING ANDOPERATING THE SAME 审中-公开
标题翻译：含有碳或氮的二极体的非挥发性记忆体装置及其制备方法
公开(公告)号：WO2009002476A3
公开(公告)日：2009-03-05
申请号：PCT/US2008007801
申请日：2008-06-23
申请人： SANDISK 3D LLC , HERNER S BRAD , CLARK MARK H , KUMAR TANMAY
发明人： HERNER S BRAD , CLARK MARK H , KUMAR TANMAY
IPC分类号： H01L27/102 , G11C11/36 , H01L27/06 , H01L29/04 , H01L29/161 , H01L29/167 , H01L29/26 , H01L29/861 , H01L29/868
CPC分类号： H01L29/868 , G11C11/5692 , G11C17/06 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021 , H01L29/04 , H01L29/161 , H01L29/167 , H01L29/66136 , H01L29/8615
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode (2) which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration. The carbon and/or nitrogen is introduced for example into the intrinsic region (6) of a p-i-n diode (4,6,8).
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管（2），其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。将碳和/或氮引入例如p-i-n二极管（4,6,8）的本征区域（6）中。

9. 发明申请

WO2007126679A3 HETEROJUNCTION DEVICE COMPRISING A SEMICONDUCTOR AND A RESISTIVITY-SWITCHING OXIDE OR NITRIDE 审中-公开
标题翻译：包含半导体和电阻率切换氧化物或氮化物的异质结器件
公开(公告)号：WO2007126679A3
公开(公告)日：2008-04-24
申请号：PCT/US2007007155
申请日：2007-03-22
申请人： SANDISK 3D LLC , KUMAR TANMAY , HERNER S BRAD
发明人： KUMAR TANMAY , HERNER S BRAD
IPC分类号： H01L27/102 , H01L21/336 , H01L21/84 , H01L27/06 , H01L27/12 , H01L29/417 , H01L29/737 , H01L29/861 , H01L29/868
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention a metal oxide or nitride compound which is a wide-i band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heteroj unction. This p-n heteroj unction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer (118), while the rest of the diode is formed of a silicon or silicon-germanium resistor; for example a diode may include a heavily doped n-type silicon region (4), an intrinsic silicon region (6), and a nickel oxide layer (118) serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monc-lithic three dimensional memory array.
摘要翻译：在本发明中，作为宽-i带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。这种p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层（118），而二极管的其余部分由硅或硅 - 锗电阻器形成; 例如二极管可以包括重掺杂的n型硅区（4），本征硅区（6）和用作p型端子的氧化镍层（118）。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单晶三维存储器阵列中。

10. 发明申请

WO2009008919A3 LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：向上指向具有大且均匀电流的P-I-N二极管的大阵列及形成相同的方法
公开(公告)号：WO2009008919A3
公开(公告)日：2009-05-22
申请号：PCT/US2008003975
申请日：2008-03-26
申请人： SANDISK 3D LLC , HERNER S BRAD
发明人： HERNER S BRAD
IPC分类号： H01L27/102
CPC分类号： H01L45/122 , B82Y10/00 , G11C13/0007 , G11C17/16 , G11C2213/16 , G11C2213/32 , G11C2213/71 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/149 , H01L45/16 , Y10S977/742 , Y10S977/842
摘要： An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate suicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array. Methods of forming a population of upward-pointing p-i-n diodes and numerous other aspects are also disclosed.
摘要翻译：公开了由沉积的硅，锗或硅锗形成的向上指向的p-i-n二极管。该二极管具有底部重掺杂P型区域，中间本征或轻掺杂区域以及顶部重掺杂N型区域。顶部重掺杂p型区域掺杂有砷，并且二极管的半导体材料与适当的硅化物，锗化物或硅化锗化物接触结晶。当施加超过二极管导通电压的电压时，可以形成大量的这种向上指向的二极管，在阵列上具有出色的电流均匀性。该二极管有利地用于单片三维存储器阵列中。还公开了形成向上指向的p-i-n二极管群的方法以及许多其他方面。

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