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11. 发明专利

BR7204708D0 未知
公开(公告)号：BR7204708D0
公开(公告)日：1973-07-10
申请号：BR470872
申请日：1972-07-14
申请人： IBM
发明人： KELLER G , OLDERDISSEN U
IPC分类号： G11C11/411 , G11C11/414 , G11C11/416 , H03K3/037 , H03K3/286 , H03K3/2885 , H03K19/32

12. 发明专利

SE325929B 未知
公开(公告)号：SE325929B
公开(公告)日：1970-07-13
申请号：SE44067
申请日：1967-01-12
申请人： IBM
发明人： BOLT M , NICK H
IPC分类号： H03K19/00 , H03K19/32
摘要： 1,104,142. Logic circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. 4 Jan., 1967 [13 Jan., 1966], No. 446/67. Heading H3T. A logic circuit includes a strip transmission line 14 to which is coupled, by means of directional couplers, a plurality of inputs A-H and an output 20 towards which the inputs are directed and from which is obtained a logical function of the inputs. In the Exclusive OR circuit shown, logical " 1 " inputs are represented on inputs A-D by a positive signal and on inputs E-H by a negative signal. The logical function obtained from inputs B, C, F, G, all equidistant from point 20, provides an output of 20 of either an Exclusive OR signal (should an odd number of inputs B, C, F, G simultaneously receive a " 1 " signal) of a positive or negative " one " level depending on whether the greater number of input signals are positive or negative, or the complement of the Exclusive OR (should there be an even number of input signals) of a zero or a positive or negative " two " level depending on how the input signals cancel or add. Further inputs e.g. A, E, D, H may be provided, supplying further Exclusive OR functions at point 20, but all at slightly different times. The train of Exclusive OR functions are detected at 25, the Complement of Exclusive OR being rejected and the positive and negative Exclusive OR signals being combined, and then counted at 30, an odd number providing an output at 13 representing the Exclusive OR function, and an even number providing a signal representing the Complement of Exclusive OR function, of all the inputs A-H. The detector may comprise two biased diode circuits, one to pass only positive " one " level signals, and the other to pass only negative " one " level signals, and a common emitter stage to invert the output of one of these diode circuits so that the outputs of both circuits may be combined.

13. 发明专利

CH465008A Verfahren zum Betrieb einer EXKLUSIV-ODER-Schaltung mit Speicherung einer Eingangsvariablen 未知
公开(公告)号：CH465008A
公开(公告)日：1968-11-15
申请号：CH866966
申请日：1966-06-15
申请人： INT STANDARD ELECTRIC CORP
发明人： ORTWIN FEUSTEL
IPC分类号： H03K17/82 , H03K19/32 , H03K19/16

14. 发明专利

SU790340A1 EXCLUSIVE OR LOGIC ELEMENT BASED ON CMDS-TRANSISTORS 未知
公开(公告)号：SU790340A1
公开(公告)日：1980-12-23
申请号：SU2710681
申请日：1979-01-10
申请人： GRIBOV YURIJ , SHAFRANSKIJ LEOPOLD V , YAKUSHEV IVAN D
发明人： GRIBOV YURIJ , SHAFRANSKIJ LEOPOLD V , YAKUSHEV IVAN D
IPC分类号： H03K19/21 , H03K19/32

15. 发明专利

DE1942420C3 未知
公开(公告)号：DE1942420C3
公开(公告)日：1980-06-12
申请号：DE1942420
申请日：1969-08-20
申请人： TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA (JAPAN)
发明人： SUZUKI, YASOJI, KAWASAKI (JAPAN)
IPC分类号： H03K19/0944 , H03K19/21 , H03K19/32 , H03K19/08
摘要： 1,252,036. F.E.T. logic circuits. TOKYO SHIBAURA ELECTRIC CO. Ltd. 15 Aug., 1969 [20 Aug., 1968], No. 40908/69. Heading H3T. An exclusive OR circuit consists of two F.E.T.'s 3, 4 interconnected as shown in block 1, Fig. 1, and inverters such as for example F.E.T.'s 6, 7 feeding inputs a, b to the sources A, B of the F.E.T.'s 3, 4, there being impedances, such as F.E.T.'s 5, 8, 9, respectively connecting the inputs and output S of block 1 to a supply voltage E. The circuit is integrated; and the use of the inverter stages is said to reduce the risk of erroneous operation when several F.E.T. circuits 1 are integrated on the same chip and have consequently similar threshold voltages which are comparable with the sum of the voltage drop across a preceding F.E.T. and its input source voltage.

16. 发明专利

DE2902112A1 未知
公开(公告)号：DE2902112A1
公开(公告)日：1979-09-06
申请号：DE2902112
申请日：1979-01-19
申请人： ANVAR
发明人： JORGENSEN PIERRE
IPC分类号： H03F3/343 , G06F7/38 , G06F7/50 , G06G7/163 , H01L21/82 , H01L27/06 , H01L27/10 , H01L27/118 , H03F3/18 , H03F3/34 , H03K3/02 , H03K3/027 , H03K3/282 , H03K3/284 , H03K3/2893 , H03K4/06 , H03K7/02 , H03K7/04 , H03K7/06 , H03K9/02 , H03K17/00 , H03K17/30 , H03K17/60 , H03K17/687 , H03K19/00 , H03K19/08 , H03K19/173 , H03K19/21 , H03L7/00 , H01L25/00 , H03K1/16 , H03K3/295 , H03K19/32

17. 发明专利

AU500170B2 PARALLEL CONNECTION OF FETS 未知
公开(公告)号：AU500170B2
公开(公告)日：1979-05-10
申请号：AU1465076
申请日：1976-06-04
申请人： IBM
发明人： FREEMAN L B , INCERTO R J , PETROSKY J A JR
IPC分类号： G11C11/412 , H01L21/8236 , H01L27/088 , H01L29/78 , H03K3/356 , H03K17/00 , H03K17/041 , H03K19/017 , H03K19/0185 , H03K19/0944 , H03K19/21 , H03K19/08 , H03K19/32 , H01L29/80 , H01L27/06 , G11C11/40 , H03K19/30 , H03K19/24
摘要： A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.

18. 发明专利

GB1494471A LOGIC GATES EMPLOYING FIELD-EFFECT TRANSISTORS 未知
公开(公告)号：GB1494471A
公开(公告)日：1977-12-07
申请号：GB3006577
申请日：1974-11-21
申请人： TEXAS INSTRUMENTS LTD
IPC分类号： H03K19/094 , H03K19/0944 , H03K19/21 , H03K9/08 , H03K19/32
摘要： 1494471 FET logic circuits TEXAS INSTRUMENTS Ltd 21 Nov 1974 30065/77 Divided out of 1492589 Heading H3T In a logic gate having first and second impedances 25, 26, Fig. 1, connected between gates and connected sources of FET's 32, 33, first and second input terminals 23, 24 are connected to respective gates of the FET's, an output terminal 31 is connected to the drains of the FET's and the first and second impedances are so arranged as to provide, in operation, direct current paths from each input terminal to the sources of the FET's without substantially shunting the first and second input terminals. The impedances can be resistors or semi-conductor diodes. Fig. 1 shows P-channel MOS transistors which function as an exclusive OR gate. A further MOS transistor may be added to provide a three input gate (Fig. 2, not shown). P- channel junction FET's (Fig. 4, not shown) can replace the MOSFET's. N-channel junction FET's may be used in place of the MOSFET's and the diodes 25 and 26 are reversed so as to form an exclusive NOR gate (Fig. 3, not shown). The output of one logic gate may be connected to one input of a next logic gate. The outputs of the logic gates can be connected in parallel. Integrated circuit techniques may be used.

19. 发明专利

GB1489007A LOGIC CIRCUITS 未知
公开(公告)号：GB1489007A
公开(公告)日：1977-10-19
申请号：GB2162475
申请日：1975-05-20
申请人： IBM
IPC分类号： H03K19/21 , H01L27/092 , H03K19/096 , H03K19/32
摘要： 1489007 Transistor logic circuits INTERNATIONAL BUSINESS MACHINES CORP 20 May 1975 [28 June 1974] 21624/75 Heading H3T A logic circuit, e.g. an exclusive OR, comprises a pair of MOSFETs 21, 22 of the same conductivity type coupled between a first supply voltage terminal 25 and an output 26 and an inverter formed by one of the MOSFETs 21 connected adjacent to one of the supply voltage terminals 25 and an additional MOSFET 36 of opposite conductivity type, connected to the other supply voltage terminal 31. In the exclusive OR circuit shown, the inputs are supplied to A, B and the inverse forms A, B of the input are derived by inverters comprising MOSFETs 21, 36 and 23, 38. The substrates of the N-type MOSFETs are connected to ground whereas those of the P-type are connected to +V. By using transistors 21, 23, which are part of a known exclusive OR circuit as parts of the inverter, two MOSFETs are saved. Fig. 1 (not shown) depicts a cross-section of an integrated circuit comprising two MOSFETs.

20. 发明专利

DE1942420B2 未知
公开(公告)号：DE1942420B2
公开(公告)日：1976-05-13
申请号：DE1942420
申请日：1969-08-20
IPC分类号： H03K19/0944 , H03K19/21 , H03K19/32
摘要： 1,252,036. F.E.T. logic circuits. TOKYO SHIBAURA ELECTRIC CO. Ltd. 15 Aug., 1969 [20 Aug., 1968], No. 40908/69. Heading H3T. An exclusive OR circuit consists of two F.E.T.'s 3, 4 interconnected as shown in block 1, Fig. 1, and inverters such as for example F.E.T.'s 6, 7 feeding inputs a, b to the sources A, B of the F.E.T.'s 3, 4, there being impedances, such as F.E.T.'s 5, 8, 9, respectively connecting the inputs and output S of block 1 to a supply voltage E. The circuit is integrated; and the use of the inverter stages is said to reduce the risk of erroneous operation when several F.E.T. circuits 1 are integrated on the same chip and have consequently similar threshold voltages which are comparable with the sum of the voltage drop across a preceding F.E.T. and its input source voltage.

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