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1. 发明授权

US3747027A Directional coupler switch wherein stripline ground conductor is moved relative to stripline coupling conductors 失效
标题翻译：方向连接器开关，其中带状接地导体相对于带状连接导体移动
公开(公告)号：US3747027A
公开(公告)日：1973-07-17
申请号：US3747027D
申请日：1972-07-07
申请人： IBM
发明人： BOLT M , UBERBACHER E
IPC分类号： H01P1/12 , H03K17/92 , H01P1/10 , H01P5/14
CPC分类号： H03K17/92 , H01P1/127
摘要： A directional coupler electric switch is provided having a housing circuit half and a housing cap half. A circuit card located within the housing circuit half has a stripline directional coupler circuit on the outer side and a grounding surface on the inner side. A second circuit card located within the housing cap half has a grounding circuit on the inner side. Connecting means are provided for the circuits within the housing at an edge thereof. The housing circuit half and the housing cap half are engaged so that the stripline directional coupler circuit is between the first and second circuit cards. The circuit card in the housing cap half is adapted to move relative to the other circuit card in the other housing half such that the grounding circuit can be moved into and out of coupling relationship with the stripline directional coupler circuit.
摘要翻译：定向耦合器电开关设置有壳体电路半部和壳体盖半部。位于壳体电路半部内的电路卡在外侧具有带状线定向耦合器电路，在内侧具有接地表面。位于外壳盖半部内的第二电路卡在内侧具有接地电路。为外壳内的电路在其边缘设置连接装置。壳体电路半部和壳体帽半部接合，使得带状线定向耦合器电路位于第一和第二电路卡之间。外壳盖半部中的电路卡适于相对于另一个外壳半部中的另一个电路卡移动，使得接地电路可以移动进入和退出与带状线定向耦合器电路的耦合关系。

2. 发明专利

SE325929B 未知
公开(公告)号：SE325929B
公开(公告)日：1970-07-13
申请号：SE44067
申请日：1967-01-12
申请人： IBM
发明人： BOLT M , NICK H
IPC分类号： H03K19/00 , H03K19/32
摘要： 1,104,142. Logic circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. 4 Jan., 1967 [13 Jan., 1966], No. 446/67. Heading H3T. A logic circuit includes a strip transmission line 14 to which is coupled, by means of directional couplers, a plurality of inputs A-H and an output 20 towards which the inputs are directed and from which is obtained a logical function of the inputs. In the Exclusive OR circuit shown, logical " 1 " inputs are represented on inputs A-D by a positive signal and on inputs E-H by a negative signal. The logical function obtained from inputs B, C, F, G, all equidistant from point 20, provides an output of 20 of either an Exclusive OR signal (should an odd number of inputs B, C, F, G simultaneously receive a " 1 " signal) of a positive or negative " one " level depending on whether the greater number of input signals are positive or negative, or the complement of the Exclusive OR (should there be an even number of input signals) of a zero or a positive or negative " two " level depending on how the input signals cancel or add. Further inputs e.g. A, E, D, H may be provided, supplying further Exclusive OR functions at point 20, but all at slightly different times. The train of Exclusive OR functions are detected at 25, the Complement of Exclusive OR being rejected and the positive and negative Exclusive OR signals being combined, and then counted at 30, an odd number providing an output at 13 representing the Exclusive OR function, and an even number providing a signal representing the Complement of Exclusive OR function, of all the inputs A-H. The detector may comprise two biased diode circuits, one to pass only positive " one " level signals, and the other to pass only negative " one " level signals, and a common emitter stage to invert the output of one of these diode circuits so that the outputs of both circuits may be combined.

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