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1. 发明专利

DE1942420C3 未知
公开(公告)号：DE1942420C3
公开(公告)日：1980-06-12
申请号：DE1942420
申请日：1969-08-20
申请人： TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA (JAPAN)
发明人： SUZUKI, YASOJI, KAWASAKI (JAPAN)
IPC分类号： H03K19/0944 , H03K19/21 , H03K19/32 , H03K19/08
摘要： 1,252,036. F.E.T. logic circuits. TOKYO SHIBAURA ELECTRIC CO. Ltd. 15 Aug., 1969 [20 Aug., 1968], No. 40908/69. Heading H3T. An exclusive OR circuit consists of two F.E.T.'s 3, 4 interconnected as shown in block 1, Fig. 1, and inverters such as for example F.E.T.'s 6, 7 feeding inputs a, b to the sources A, B of the F.E.T.'s 3, 4, there being impedances, such as F.E.T.'s 5, 8, 9, respectively connecting the inputs and output S of block 1 to a supply voltage E. The circuit is integrated; and the use of the inverter stages is said to reduce the risk of erroneous operation when several F.E.T. circuits 1 are integrated on the same chip and have consequently similar threshold voltages which are comparable with the sum of the voltage drop across a preceding F.E.T. and its input source voltage.

2. 发明专利

DE2165445B2 未知
公开(公告)号：DE2165445B2
公开(公告)日：1979-07-12
申请号：DE2165445
申请日：1971-12-29
申请人： TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA (JAPAN)
发明人： SUZUKI, YASOJI, KAWASAKI (JAPAN)
IPC分类号： G11C19/18 , H03K19/096 , G11C19/28 , G11C11/40 , H03K19/08
摘要： A logical circuit arrangement is comprised by a switching circuit including a first logic unit constituted by insulated gate field effect transistors of one conductivity type channel and a second logic unit constituted by insulated gate field effect transistors of the other conductivity type channel; a shift register applied with the output switching circuit and including a plurality of bit elements, each constituted by first and second cascade connected complementary inverters which are composed of insulated gate field effect transistors of the complementary conductivity type channel; a complementary buffer circuit connected to the output from the buffer circuit to the first and second logic units; and a circuit for applying a logical input data signal, a control pulse and a complement signal of the control signal to the gate electrodes of the insulated gate field effect transistors of the switching circuit respectively for selectively switching the polarity of the logical output of the first and second logic units to supply said shift register with said input data signal or an output signal of said buffer circuit in accordance with said control pulse and the complemental pulse of the control pulse.

3. 发明专利

DE2139170C3 未知
公开(公告)号：DE2139170C3
公开(公告)日：1978-07-20
申请号：DE2139170
申请日：1971-07-30
申请人： TOKYO SHIBAURA ELECTRIC CO., LTD., KAWASAKI, KANAGAWA (JAPAN)
发明人： SUZUKI, YASOJI, KAWASAKI (JAPAN)
IPC分类号： G06F7/501 , G06F7/50
摘要： A binary full adder-subtractor includes a first logic circuit which is supplied with binary digital signals respectively corresponding to an operand and an operator; a second logic unit which is supplied with the outputs of the first logic unit and a first carrying or borrowing signal of a preceding digit; and a gating circuit including AND gate circuits and OR gate circuits and which is supplied with binary digital signals respectively corresponding to the operand, the first carrying or borrowing signal, the output of the first logic unit and an operating signal for starting an addition or subtraction operation, to provide a second carrying or borrowing signal for a succeeding digit.

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