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11. 发明授权

US06836009B2 Packaged microelectronic components 有权
标题翻译：封装微电子元件
公开(公告)号：US06836009B2
公开(公告)日：2004-12-28
申请号：US10230761
申请日：2002-08-28
申请人： Eng Meow Koon , Low Siu Waf , Chan Min Yu , Chia Yong Poo , Ser Bok Leng , Zhou Wei
发明人： Eng Meow Koon , Low Siu Waf , Chan Min Yu , Chia Yong Poo , Ser Bok Leng , Zhou Wei
IPC分类号： H01L2941
CPC分类号： H01L21/4842 , H01L22/10 , H01L23/3107 , H01L23/3114 , H01L23/4951 , H01L23/49551 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/03 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/16 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/85399 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.
摘要翻译：微电子部件封装包括耦合到微电子部件并且具有向外延伸超过密封剂的外围边缘的暴露长度的多个电引线。多个端子可以位于密封剂的端面附近，并且这些端子可以电耦合到相同的引线。这可以有助于使用引线作为常规引线封装将微电子部件连接到基板。然而，这些端子可以促进引线封装与一个或多个额外的微电子部件例如BGA封装的堆叠。

12. 发明授权

US06639294B2 Semiconductor device having a device formation region protected from a counterelectromotive force 失效
标题翻译：具有防止反电动势的装置形成区域的半导体装置
公开(公告)号：US06639294B2
公开(公告)日：2003-10-28
申请号：US10191472
申请日：2002-07-10
申请人： Keiichi Furuya , Fumitoshi Yamamoto , Tomohide Terashima
发明人： Keiichi Furuya , Fumitoshi Yamamoto , Tomohide Terashima
IPC分类号： H01L2941
CPC分类号： H01L21/761 , H01L27/0623
摘要： A semiconductor device includes an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.
摘要翻译：半导体器件包括在P型硅衬底上形成的外延层; 用于将外延层划分成构成器件形成区域的N外延层的P +扩散层和构成无效区域的N外延层; 以及用于将N外延层（无效区域）电连接到P +扩散层的铝线。由于N外延层（无效区域）的电位可以等于P +扩散层的电位，所以即使向电子提供电子，也可以防止从P +扩散层向无效区域的电子供给通过由具有电感L的负载产生的反电动势形成区域。

13. 发明授权

US06465894B2 Semiconductor device having bed structure underlying electrode pad 有权
标题翻译：半导体器件具有位于电极焊盘下方的床结构
公开(公告)号：US06465894B2
公开(公告)日：2002-10-15
申请号：US09907659
申请日：2001-07-19
申请人： Noboru Koike
发明人： Noboru Koike
IPC分类号： H01L2941
CPC分类号： H01L24/05 , H01L21/76229 , H01L24/03 , H01L24/06 , H01L24/11 , H01L2224/02166 , H01L2224/0401 , H01L2224/05556 , H01L2224/13099 , H01L2224/78301 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01074 , H01L2924/05042
摘要： A semiconductor device has: a semiconductor substrate having a surface which has a predetermined pattern, in which an insulating layer is embedded; an interlayer insulator film formed on the substrate, the interlayer insulator film having a protective coat for protecting the substrate; and an electrode formed on the interlayer insulator film. In addition, a method for manufacturing a semiconductor device comprises the steps of: forming a semiconductor substrate having a surface which has a groove in which an insulating layer is embedded; forming a protective coat for protecting the surface of the semiconductor substrate, on the upper surface of the insulating layer embedded in the groove; and forming an electrode on the protective coat. According to the semiconductor device and the method for manufacturing the same, it is possible to more sufficiently planarize the surface of the insulating layer by the rotary polishing method, and it is possible to decrease the bonding damage applied to a underlayer portion serving as a bed of the semiconductor device when carrying out the wire bonding.
摘要翻译：半导体器件具有：具有嵌入有绝缘层的具有预定图案的表面的半导体衬底; 形成在所述基板上的层间绝缘膜，所述层间绝缘膜具有用于保护所述基板的保护层; 以及形成在层间绝缘膜上的电极。此外，半导体器件的制造方法包括以下步骤：形成具有表面的半导体衬底，该表面具有嵌入绝缘层的沟槽; 在嵌入槽内的绝缘层的上表面上形成保护半导体衬底表面的保护层; 并在保护层上形成电极。根据半导体装置及其制造方法，可以通过旋转研磨方法更充分地平坦化绝缘层的表面，并且可以减少施加到用作床的下层部分的接合损伤的半导体器件。

14. 发明授权

US06316827B1 Semiconductor device having improved temperature distribution 有权
标题翻译：具有改善的温度分布的半导体器件
公开(公告)号：US06316827B1
公开(公告)日：2001-11-13
申请号：US09151276
申请日：1998-09-11
申请人： Kazunori Asano , Kouji Ishikura
发明人： Kazunori Asano , Kouji Ishikura
IPC分类号： H01L2941
CPC分类号： H01L29/41725 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of the present invention includes ohmic source plate electrodes, gate plate electrodes, and drain plate electrodes in parallel from each other in a heat generating region various designs are used to more evenly distribute heat generated in the semiconductor device. A first example has gold-plate electrodes formed on the respective source and drain plate electrodes in parallel with the ohmic plate electrodes. The gold-plate electrode arranged at the central portion of the heat generating region plate electrodes has the widest width and gold-plate electrodes arranged toward the center portion to the peripheral portion of the heat generating region narrow gradually. By the structure mentioned above, the semiconductor device of the present invention has uniform temperature distribution in a heat generating region. A second example uses a plurality of stripe plates perpendicular to the ohmic plate electrodes. Those stripe plates are of varying separation distances, being closer at the center of the heat generating region. A third example varies the thickness of the semiconductor substrate inversely proportional to the distance from the center of the heat generating region.
摘要翻译：本发明的半导体器件在发热区域中包括欧姆源极电极，栅极板电极和漏极电极，它们彼此平行地使用各种设计来更均匀地分布在半导体器件中产生的热量。第一示例是在与欧姆板电极平行的各个源极和漏极电极上形成金平板电极。布置在发热区域板电极的中心部分的金板电极具有最宽的宽度，并且朝着发热区域的周边部分的中心部分逐渐设置的金板电极。通过上述结构，本发明的半导体器件在发热区域中具有均匀的温度分布。第二示例使用垂直于欧姆板电极的多个条板。这些条板具有不同的间隔距离，更靠近发热区域的中心。第三示例使半导体衬底的厚度与从发热区域的中心的距离成反比变化。

15. 发明授权

US06252260B1 Electrode structure of hetero-junction intertal photo-emission inreared detector 失效
标题翻译：异质结间隔光发射不对称探测器的电极结构
公开(公告)号：US06252260B1
公开(公告)日：2001-06-26
申请号：US09105281
申请日：1998-06-26
申请人： Peiyi Chen , Peixin Qian , Ruizhong Wang
发明人： Peiyi Chen , Peixin Qian , Ruizhong Wang
IPC分类号： H01L2941
CPC分类号： H01L31/0216 , H01L31/0224 , H01L31/028 , H01L31/036 , Y02E10/547
摘要： An electrode structure of an HIP infrared detector. A HIP infrared comprises a p-type silicon substrate which has an exposed guard ring, an exposed region of the silicon substrate encompassed by the guard ring, and a silicon oxide layer covering a part of the guard ring and the silicon substrate. On the silicon substrate, a photosensitive alloy layer comprises an amorphous photosensitive alloy layer on the silicon oxide layer, and a single crystalline photosensitive alloy layer on both the part of the silicon substrate encompassed by the guard ring and the guard ring. An electrode to electrically connects the silicon substrate via the photosensitive alloy layer. Moreover, the HIP infrared further comprises a p+ Ohmic contact in the silicon substrate and another electrode to contact with the p+ Ohmic contact.
摘要翻译： HIP红外探测器的电极结构。 HIP红外线包括具有暴露的保护环的p型硅衬底，由保护环包围的硅衬底的暴露区域以及覆盖保护环和硅衬底的一部分的氧化硅层。在硅衬底上，感光合金层包括在氧化硅层上的非晶感光合金层，以及由保护环和保护环包围的硅衬底的两部分上的单晶感光合金层。一种用于通过感光合金层电连接硅衬底的电极。此外，HIP红外线还包括在硅衬底中的p +欧姆接触和另一电极与p +欧姆接触接触。

16. 发明授权

US06208008B1 Integrated circuits having reduced stress in metallization 失效
标题翻译：集成电路在金属化中具有降低的应力
公开(公告)号：US06208008B1
公开(公告)日：2001-03-27
申请号：US09260702
申请日：1999-03-02
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L2941
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

17. 发明授权

US06707074B2 Semiconductor light-emitting device and apparatus for driving the same 失效
标题翻译：半导体发光装置及其驱动装置
公开(公告)号：US06707074B2
公开(公告)日：2004-03-16
申请号：US09895213
申请日：2001-07-02
申请人： Shigeo Yoshii , Kiyoshi Ohnaka
发明人： Shigeo Yoshii , Kiyoshi Ohnaka
IPC分类号： H01L2941
CPC分类号： H01L33/30 , H01L33/06 , H01L33/32 , H01S5/3215
摘要： A semiconductor light-emitting device has first and second semiconductor layers each of a first conductivity type, a third semiconductor layer of a second conductivity type provided between the first and second semiconductor layers, and an active layer provided between the second and third semiconductor layers to emit light with charge injected therein from the second and third semiconductor layers. A graded composition layer is provided between the active layer and the third semiconductor layer to have a varying composition which is nearly equal to the composition of the active layer at the interface with the active layer and to the composition of the third semiconductor layer at the interface with the third semiconductor layer.
摘要翻译：半导体发光器件具有第一和第二半导体层，第一和第二半导体层各自具有第一导电类型，第二导电类型的第三半导体层，设置在第一和第二半导体层之间;以及有源层，设置在第二和第三半导体层之间，从第二和第三半导体层发射具有注入其中的电荷的光。在有源层和第三半导体层之间设置渐变组成层，以具有与有源层界面处的有源层的组成以及界面处的第三半导体层的组成几乎相等的变化的组成与第三半导体层。

18. 发明授权

US06576987B2 Interdigitated leads-over-chip lead frame, device, and method for supporting an integrated circuit die 有权
公开(公告)号：US06576987B2
公开(公告)日：2003-06-10
申请号：US09888885
申请日：2001-06-25
申请人： Aaron Schoenfeld , Jerry M. Brooks
发明人： Aaron Schoenfeld , Jerry M. Brooks
IPC分类号： H01L2941
CPC分类号： H01L23/49541 , H01L23/4951 , H01L23/49568 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , Y10T29/49121 , Y10T29/49169 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399
摘要： An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

19. 发明授权

US06448657B1 Structure for reducing junction spiking through a wall surface of an overetched contact via 失效
公开(公告)号：US06448657B1
公开(公告)日：2002-09-10
申请号：US09692911
申请日：2000-10-19
申请人： Fernand Dorleans
发明人： Fernand Dorleans
IPC分类号： H01L2941
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76805 , H01L21/76831 , H01L21/76876 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention pertains to a semiconductor device microstructure, and to a method of forming that microstructure, which reduces or prevents junction spiking and to a method of forming that microstructure. In particular, a semiconductor contact microstructure comprises a feature which includes a silicon base and at least one sidewall extending upward from the silicon base. The sidewall includes a silicon portion in contact with the silicon base, where the height of the silicon portion of the sidewall above the silicon base is typically less than about 0.5 &mgr;m. The sidewall also includes at least one portion which comprises a first dielectric material which is in contact with (and typically extends upward from) the silicon portion of the sidewall. Overlying at least the silicon portion of the sidewall is a layer of a second dielectric material, preferably silicon oxide. Typically, a diffusion barrier layer overlies the silicon base, the layer of second dielectric material, and at least part of the sidewall portion which is comprised of the first dielectric material. The method comprises the steps of: a) providing a semiconductor device feature which includes a silicon base and at least one sidewall extending upward from the silicon base, where the sidewall includes at least one silicon portion in contact with the silicon base, and another portion comprising a first dielectric material which is in contact with the silicon portion of the sidewall; and b) creating a layer of a second dielectric material, preferably silicon oxide, over the at least one silicon sidewall portion. The method may include additional steps: c) sputter etching to remove dielectric material from the surface of the silicon base; and d) applying a diffusion barrier material over the silicon base, the layer of second dielectric material, and at least a portion of the sidewall comprising the first dielectric material. Typically, both the first and second dielectric materials are silicon oxide.

20. 发明授权

US06369407B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06369407B1
公开(公告)日：2002-04-09
申请号：US09500462
申请日：2000-02-09
申请人： Junichi Hikita , Hiroo Mochida , Kazutaka Shibata
发明人： Junichi Hikita , Hiroo Mochida , Kazutaka Shibata
IPC分类号： H01L2941
CPC分类号： H01L22/32 , H01L2224/05554
摘要： A semiconductor device has a semiconductor substrate, an internal circuit formed on the semiconductor substrate, a connection pad formed on the semiconductor substrate and connected to the internal circuit, and a test pad formed on the semiconductor substrate so as to be connected to the connection pad and used for functional testing of the internal circuit. The semiconductor substrate has a bonding region provided on the surface thereof so as to allow another semiconductor substrate to be superposed thereon by being bonded thereto, with the connection pad formed inside the bonding region and the test pad formed outside the bonding region.
摘要翻译：半导体器件具有半导体衬底，形成在半导体衬底上的内部电路，形成在半导体衬底上并连接到内部电路的连接焊盘和形成在半导体衬底上的测试焊盘，以便连接到连接焊盘并用于内部电路的功能测试。半导体衬底具有设置在其表面上的接合区域，以便通过将其它半导体衬底与其结合在一起，其中连接焊盘形成在接合区域内部，并且测试焊盘形成在接合区域外部。

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