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11. 发明授权

US06183141B2 Minimizing program code storage for performing regular and repetitive operations in a programmable processor 失效
标题翻译：最小化程序代码存储，以在可编程处理器中执行常规和重复操作
公开(公告)号：US06183141B2
公开(公告)日：2001-02-06
申请号：US08603620
申请日：1996-02-21
申请人： Frédéric Dufal , Gilles Privat
发明人： Frédéric Dufal , Gilles Privat
IPC分类号： G06F922
CPC分类号： G06F9/30185
摘要： The program memory comprises a first segment (MP1) containing a succession of program words including first base words (MMA) each having a size less than the sum of the respective sizes of the control words destined for the execution units (UXi), and second base words (MMB) fewer in number than that of the first base words. Facilities sequentially extract the various program words from the first segment of the program memory. A storage facility (RG) is connected to the output of the program memory. Facilities (MXM) update the content of the storage facility at least on the basis of each extracted second base word, and computational facilities (MEB) sequentially compute certain at least of the various groups of control words, on the basis of the combining according to at least one predetermined logic relation, of the content of the storage facility and of an extracted first base word, so as to minimize the memory size of the said program code.
摘要翻译：程序存储器包括包含一系列程序字的第一段（MP1），该段包括第一基本单词（MMA），每一个都具有小于目的地为执行单元（UXi）的控制字的相应大小之和的大小，基本词（MMB）的数量少于第一个基本词。设备从程序存储器的第一段顺序提取各种程序字。存储设备（RG）连接到程序存储器的输出。设备（MXM）至少基于每个提取的第二基本词来更新存储设施的内容，并且计算设施（MEB）基于根据以下的组合依次计算各组控制字中的至少一组：存储设施的内容和所提取的第一基本字的至少一个预定的逻辑关系，以便最小化所述程序代码的存储器大小。

12. 发明授权

US06760832B2 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06760832B2
公开(公告)日：2004-07-06
申请号：US10281148
申请日：2002-10-28
申请人： Junichi Nishimoto , Hideo Maejima
发明人： Junichi Nishimoto , Hideo Maejima
IPC分类号： G06F922
CPC分类号： G06F9/3822 , G06F9/30149 , G06F9/30196 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3877 , G06F9/3885
摘要： A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.
摘要翻译：一种数据处理器，包括用于执行第一指令集的第一处理器和用于执行不同于第一指令集的第二指令集的第二处理器。当第一处理器执行第一指令集的预定指令时，第二处理器执行第二指令集的指令。第一处理器可以是精简指令集计算机（RISC）型处理器，第二处理器可以是非常长的指令字（VLIW）型处理器，第一指令集可以是RISC指令集，第二指令集可以是 VLIW指令集。由第一处理器执行的RISC指令集的预定指令可以是使分支指向存储VLIW指令的特定地址空间的分支指令。此后，VLIW型处理器执行特定地址空间处的VLIW指令。

13. 发明授权

US06738894B1 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US06738894B1
公开(公告)日：2004-05-18
申请号：US09655465
申请日：2000-09-05
申请人： Katsumi Iwata
发明人： Katsumi Iwata
IPC分类号： G06F922
CPC分类号： G06F8/654 , G06F12/0638
摘要： To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.
摘要翻译：为了获得正确的向量地址，即使在通过总线控制器27将内置RAM13的一部分移动到向量地址区域时，在内置ROM18中的数据的擦除或编程期间发生中断。由此，防止在内置ROM 18的板载编程时提高系统的安全性。

14. 发明授权

US06718455B1 Multimedia-instruction acceleration device and method thereof 有权
标题翻译：多媒体指令加速装置及其方法
公开(公告)号：US06718455B1
公开(公告)日：2004-04-06
申请号：US09614540
申请日：2000-07-12
申请人： Nai-Sheng Cheng
发明人： Nai-Sheng Cheng
IPC分类号： G06F922
CPC分类号： G06F9/30021 , G06F9/3885
摘要： The present invention proposes a multimedia-instruction acceleration device and a method thereof, which uses instruction strings having a floating-point value check field to execute commands of single-instruction/multi-data format. The present invention can effectively save executing time and simplify numerical calculation process, and can fully exploit memory space to achieve the object of increasing acceleration operation and execution of 3D multimedia instructions. Moreover, an instruction of another mode can be added among the multi-data pertaining to a single 3D instruction so that another program such as a voice-playing program can be executed during the process of 3D acceleration operation. The performance of the multimedia program can thus be enhanced.
摘要翻译：本发明提出了一种多媒体指令加速装置及其方法，其使用具有浮点值检查字段的指令串来执行单指令/多数据格式的命令。本发明可以有效地节省执行时间，简化数值计算过程，可以充分利用存储空间来实现增加3D多媒体指令的加速操作和执行的对象。此外，可以在与单个3D指令相关的多数据中添加另一模式的指令，使得可以在3D加速操作的处理期间执行诸如语音播放程序的另一程序。因此可以提高多媒体节目的表现。

15. 发明授权

US06408376B1 Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously 失效
标题翻译：用于指令集体系结构的方法和装置，用于同时执行主和阴影数字信号处理子指令
公开(公告)号：US06408376B1
公开(公告)日：2002-06-18
申请号：US09652100
申请日：2000-08-30
申请人： Kumar Ganapathy , Ruban Kanapathipillai
发明人： Kumar Ganapathy , Ruban Kanapathipillai
IPC分类号： G06F922
CPC分类号： G06F9/3877 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30192 , G06F9/381 , G06F9/382 , G06F9/383 , G06F9/3842 , G06F9/3853 , G06F9/3885 , G06F17/10
摘要： Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. In one embodiment, a single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. The DSP operations, in one embodiment, include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX), and a no operation instruction (NOP). Each signal processing unit includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. Control logic is utilized to control shadow selectors of each signal processing unit to select delayed data (specified by the shadow DSP sub-instruction) for use by the shadows stages of the signal processing units. In this way, the present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction thereby performing four operations per single instruction cycle.
摘要翻译：公开了针对数字信号处理（DSP）应用定制的专用信号处理器（ASSP）的方法，装置和指令集架构（ISA）。采用ASSP实现的指令集架构适用于DSP算法结构。在一个实施例中，单个DSP指令包括一对子指令：主DSP子指令和阴影DSP子指令。主要和阴影DSP子指令都是在一个指令周期内执行两个操作的二进制DSP指令。在一个实施例中，DSP操作包括乘法指令（MULT），加法指令（ADD），最小化/最大化指令（MIN / MAX）和无操作指令（NOP）。每个信号处理单元包括基于当前数据执行主DSP子指令的初级阶段和阴影阶段，以基于本地存储在信号处理单元的寄存器内的延迟数据来同时执行阴影DSP子指令。控制逻辑用于控制每个信号处理单元的阴影选择器，以选择由信号处理单元的阴影级使用的延迟数据（由阴影DSP子指令指定）。以这种方式，本发明通过使用单个DSP指令同时执行主DSP子指令（基于当前数据）和阴影DSP子指令（基于延迟本地存储的数据）来有效地执行DSP指令，从而每单个执行四个操作指令周期。

16. 发明授权

US06314485B1 Automatic status register 失效
标题翻译：自动状态寄存器
公开(公告)号：US06314485B1
公开(公告)日：2001-11-06
申请号：US09100892
申请日：1998-06-22
申请人： David Lawson Potts
发明人： David Lawson Potts
IPC分类号： G06F922
CPC分类号： G06F13/126 , H04L7/0004 , H04L7/0025 , H04L7/0029 , H04L7/0278
摘要： One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g., by a write to a write direction extra bits register addressable through a specific input/output (I/O) location. The extra bits are tacked on to a subsequent write cycle in the digital serial interface, e.g., in the AC '97 link, to write an excess length data word. In the read direction, each read cycle places excess bits in a read direction extra bits register for reading in a subsequent read cycle. Another aspect of the invention provides an automatic status register which provides, e.g., automatic creation of a TAG Phase in time slot 0 of an AC '97 link using, e.g., a write enable signal to various resources in the digital serial interface, e.g., write enable signals to time slot registers.
摘要翻译：本发明的一个方面提供一种用于数字串行接口的封隔器解包器（PUP），其允许多个处理器访问与数字串行接口有关的串行数据流的时隙寄存器。配置寄存器由多个处理器中的一个处理器或每个处理器维护以仲裁对各个时隙寄存器的访问。本发明的另一方面允许一个或多个处理器有效地访问和/或写入诸如时隙寄存器的资源，而不是处理器相应的数据总线允许的宽度。为读写方向数据总线中的至少一个维持额外位寄存器。额外的比特对应于从一个宽度的数据总线改变到较窄宽度的数据总线时常常被忽略的最低有效位。写入方向上的额外位可通过例如通过写特定输入/输出（I / O）位置写入写入方向额外位寄存器来访问。数字串行接口中的额外位被固定到例如AC '97链路中的后续写周期以写入超长数据字。在读取方向，每个读取周期将多余的位放置在读取方向的额外位寄存器中，以便在随后的读取周期中进行读取。本发明的另一方面提供一种自动状态寄存器，其提供例如使用例如对数字串行接口中的各种资源的写使能信号来自动创建AC'97链路的时隙0中的TAG相位，例如，将使能信号写入时隙寄存器。

17. 发明授权

US06192467B1 Executing partial-width packed data instructions 失效
公开(公告)号：US06192467B1
公开(公告)日：2001-02-20
申请号：US09053000
申请日：1998-03-31
申请人： Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F922
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/3822 , G06F9/384
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.

18. 发明授权

US06813702B1 Methods and apparatus for generating effective test code for out of order super scalar microprocessors 失效
标题翻译：用于产生有序超标量微处理器的有效测试代码的方法和装置
公开(公告)号：US06813702B1
公开(公告)日：2004-11-02
申请号：US09106691
申请日：1998-06-29
申请人： Carl Geisler Ramey , Daniel Lawrence Leibholz
发明人： Carl Geisler Ramey , Daniel Lawrence Leibholz
IPC分类号： G06F922
CPC分类号： G06F9/3851 , G06F11/261
摘要： A technique for producing a test executable in a computer. The technique involves forming multiple instruction streams. The technique further involves dividing the multiple instruction streams into portions, and generating a combined instruction stream having the portions interleaved. Additionally, the technique involves creating a test executable from the combined instruction stream. The test executable can be used for testing a simulated processor in a computer. In particular, the test executable is loaded. Then, the test executable is run through the simulated processor to generate processor results and through a reference model to generate reference results. The processor results and the reference results are compared to determine whether the simulated processor operates correctly.
摘要翻译：一种用于在计算机中生成测试可执行文件的技术。该技术涉及形成多个指令流。该技术还包括将多个指令流分成多个部分，并产生具有交错部分的组合指令流。此外，该技术涉及从组合的指令流创建测试可执行文件。测试可执行文件可用于测试计算机中的模拟处理器。特别是，加载测试可执行文件。然后，测试可执行文件通过模拟处理器运行，以生成处理器结果，并通过参考模型生成参考结果。比较处理器结果和参考结果，以确定模拟处理器是否正常运行。

19. 发明授权

US06775766B2 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06775766B2
公开(公告)日：2004-08-10
申请号：US09796040
申请日：2001-02-28
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

20. 发明授权

US06611909B1 Method and apparatus for dynamically translating program instructions to microcode instructions 有权
标题翻译：用于将程序指令动态地转换为微代码指令的方法和装置
公开(公告)号：US06611909B1
公开(公告)日：2003-08-26
申请号：US09201855
申请日：1998-12-01
申请人： Tobias Roos , Dan Halvarsson , Tomas Jonsson
发明人： Tobias Roos , Dan Halvarsson , Tomas Jonsson
IPC分类号： G06F922
CPC分类号： G06F9/30181 , G06F9/261 , G06F9/30145 , G06F9/30189 , G06F9/30196 , G06F11/3024 , G06F11/3055 , G06F11/3466
摘要： In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal, influencing the translation process in the instruction decoding unit. These state signals are added to the operation code of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table, the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt. The dynamic decoding can for a trace enabling signal be used for switching on and off a trace function. In the normal case, when tracing is not desired, no microinstructions supporting the trace function have to executed and thereby the performance and in particular the speed of the computer system will be increased.
摘要翻译：在计算机系统中，用于将程序指令转换为微代码指令的指令解码单元动态地进行操作。因此，单元接收指示计算机的状态的状态信号，例如跟踪使能信号，影响指令解码单元中的转换处理。这些状态信号被添加到要解码的程序指令的操作代码中，因此程序指令的操作代码被扩展并用作转换表的输入，程序指令的扩展操作代码被视为表中的一个字段。因此，对于不同的状态信号值，对于程序指令的相同操作代码寻址的字段的地址和因此的内容可以是不同的。因此，通常情况下，状态信号使指令译码器改变其翻译算法，使得解码器可根据信号采用的状态对不同的操作码进行解码。动态解码可以用于跟踪启用信号用于打开和关闭跟踪功能。在正常情况下，当不期望跟踪时，不需要执行支持跟踪功能的微指令，从而提高计算机系统的性能，特别是速度。

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