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11. 发明申请

US20110150159A1 CLOCK-FORWARDING TECHNIQUE FOR HIGH-SPEED LINKS 有权
标题翻译：用于高速链接的时钟转发技术
公开(公告)号：US20110150159A1
公开(公告)日：2011-06-23
申请号：US12642348
申请日：2009-12-18
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H04L7/00
CPC分类号： H04L25/247 , H03L7/0805 , H04L7/0012
摘要： A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.
摘要翻译：描述了诸如时钟再生和乘法电路的中继器电路。在该中继器电路中，时钟倍增器单元（CMU）基于在链路上接收到的转发时钟信号产生内部时钟信号。此外，中继器电路中的相位插值器（PI）基于转发的时钟信号和内部时钟信号来提供输出时钟信号。注意，CMU和PI滤波器减少转发的时钟信号和内部时钟信号中的周期到周期抖动，并且输出时钟信号具有作为转发的时钟信号的相位的加权平均的相位，以及内部时钟信号。此外，可以基于链路上的位置或位置来调整所转发的时钟信号和内部时钟信号的相对权重（即，相位平均和抖动滤波的量）。

12. 发明授权

US4910755A Regenerator/synchronizer method and apparatus for missing-clock timing messages 失效
标题翻译：用于缺少时钟定时消息的再生器/同步器方法和装置
公开(公告)号：US4910755A
公开(公告)日：1990-03-20
申请号：US310825
申请日：1989-02-14
申请人： Stephen L. Knapp
发明人： Stephen L. Knapp
IPC分类号： H04L7/033 , H04L25/24
CPC分类号： H04L7/0331 , H04L25/247
摘要： In a bit-serial type data transmission system using the interruption of clock pulses in the timing message to identify separate data word groups in the data messages, a method and apparatus for recovering the transmitter clock oscillator frequency and thereby identifying the interruption interval. The method and apparatus in addition provide signals which may be employed to control the reception of the serial data word groups, to indicate the availability of the data groups as bit-parallel words, and to provide for the retransmission of the received data word groups or the transmission of other word groups.
摘要翻译：在使用定时消息中的时钟脉冲中断的位串行数据传输系统中，识别数据消息中的分离的数据字组，用于恢复发射机时钟振荡器频率并由此识别中断间隔的方法和装置。该方法和装置另外提供可用于控制串行数据字组的接收的信号，以指示数据组作为位并行字的可用性，并提供对所接收的数据字组的重传或传输其他单词组。

13. 发明授权

US4860292A Communication protocol 失效
标题翻译：通讯协议
公开(公告)号：US4860292A
公开(公告)日：1989-08-22
申请号：US85096
申请日：1987-08-13
申请人： Bruce E. Newman , Randall A. White , Steven D. DiPirro
发明人： Bruce E. Newman , Randall A. White , Steven D. DiPirro
IPC分类号： H04L1/16 , H04L25/24 , H04L29/06
CPC分类号： H04L29/06 , H04L25/247
摘要： A method of communicating between two control units includes transmitting a message from one control unit to the other, checking the message at the other control unit for proper reception, if the reception is not proper, sending a NAK signal from the other to the one control unit, if the reception is proper, sending an ACK signal from the other to the one control unit, and upon receiving an NAK at said one control unit, resending the original message.
摘要翻译：一种在两个控制单元之间进行通信的方法包括：将一个消息从一个控制单元发送到另一个控制单元，如果接收不正确，则检查另一个控制单元处的消息以进行正确接收，从另一个控制单元向一个控制器发送NAK信号单元，如果接收正确，则从另一控制单元发送ACK信号，并且在所述一个控制单元接收到NAK时，重新发送原始消息。

14. 发明授权

US4821286A Quaternary signal regenerator 失效
标题翻译：第四纪信号再生器
公开(公告)号：US4821286A
公开(公告)日：1989-04-11
申请号：US867218
申请日：1986-05-27
申请人： James F. Graczyk , John J. Ludwick , Edward S. Parsons
发明人： James F. Graczyk , John J. Ludwick , Edward S. Parsons
IPC分类号： H04L25/03 , H04L25/24 , H04L25/49 , H04L25/60
CPC分类号： H04L25/247 , H04L25/03019 , H04L25/4917
摘要： A digital signal regenerator receives a four-level input signal, amplifies, reshapes, and retimes that signal into a regenerated four-level output signal. A wide range controlled equalizer amplifies and reshapes the four-level input signal into an intermediate signal. A variable all-pass circuit varies the shape of the equalizer's phase characteristic to optimally shape the four-level signal as a function of the maximum amplitude of the four-level input signal. The reshaped four-level signal is retimed and amplified into the regenerated four-level output signal. This enable multiplying the rate at which information is transmitted for a selected pulse rate in the transmission line.
摘要翻译：数字信号再生器接收四电平输入信号，将该信号放大，重新形成并重新生成再生四电平输出信号。宽范围控制均衡器将四电平输入信号放大并重新形成中间信号。可变全通电路改变均衡器相位特性的形状，以根据四电平输入信号的最大幅度来最佳地形成四电平信号。重新整形的四电平信号被重新定时并放大到再生的四电平输出信号。这使得能够在传输线路中将所发送的信息的速率与所选脉冲速率相乘。

15. 发明授权

US11979480B2 Quadrature circuit interconnect architecture with clock forwarding 有权
公开(公告)号：US11979480B2
公开(公告)日：2024-05-07
申请号：US17933557
申请日：2022-09-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael Sperling , Daniel Mark Dreps , Erik English , Jieming Qi
IPC分类号： H04L7/00 , H04L25/00 , H04L25/24 , H04L25/40
CPC分类号： H04L7/0012 , H04L25/247
摘要： An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

16. 发明授权

US08583841B2 Digital video data relay 有权
标题翻译：数字视频数据中继
公开(公告)号：US08583841B2
公开(公告)日：2013-11-12
申请号：US12905377
申请日：2010-10-15
申请人： Henry Zeng , Ji Park
发明人： Henry Zeng , Ji Park
IPC分类号： G06F3/00 , G06F13/00 , G06F13/12
CPC分类号： H04N21/43635 , G06F3/1423 , G09G5/008 , G09G2370/10 , G09G2370/12 , H03L7/0807 , H03L7/23 , H04L25/242 , H04L25/247
摘要： A video relay circuit is provided including an input channel to receive input video data packets; a first circuit to convert the input video data packets into data for a display device; a second circuit coupled to the first circuit to retime, recondition and re-drive the data channels; an output channel to couple the video data packets into an output stream. Also provided is a video data transmission link including a video relay circuit as above and a daisy chain of video display devices including a video source; a plurality of video display devices wherein a first video display device is coupled to the source of video data, and each further video display device receives the source signal from the previous display and provides the video signal to the next display; wherein at least one of the video display devices comprises a video relay circuit as above.
摘要翻译：提供一种视频中继电路，包括用于接收输入视频数据分组的输入通道; 第一电路，用于将输入视频数据分组转换为显示设备的数据; 第二电路，耦合到所述第一电路，以重新调整和重新驱动所述数据信道; 用于将视频数据分组耦合到输出流的输出通道。还提供了包括如上所述的视频中继电路和包括视频源的视频显示设备的菊花链的视频数据传输链路; 多个视频显示装置，其中第一视频显示装置耦合到视频数据源，并且每个另外的视频显示装置接收来自先前显示的源信号，并将视频信号提供给下一个显示; 其中至少一个视频显示装置包括如上所述的视频中继电路。

17. 发明申请

US20120096509A1 DIGITAL VIDEO DATA RELAY 有权
标题翻译：数字视频数据继电器
公开(公告)号：US20120096509A1
公开(公告)日：2012-04-19
申请号：US12905377
申请日：2010-10-15
申请人： Henry ZENG , Ji PARK
发明人： Henry ZENG , Ji PARK
IPC分类号： H04N7/173
CPC分类号： H04N21/43635 , G06F3/1423 , G09G5/008 , G09G2370/10 , G09G2370/12 , H03L7/0807 , H03L7/23 , H04L25/242 , H04L25/247
摘要： A video relay circuit is provided including an input channel to receive input video data packets; a first circuit to convert the input video data packets into data for a display device; a second circuit coupled to the first circuit to retime, recondition and re-drive the data channels; an output channel to couple the video data packets into an output stream. Also provided is a video data transmission link including a video relay circuit as above and a daisy chain of video display devices including a video source; a plurality of video display devices wherein a first video display device is coupled to the source of video data, and each further video display device receives the source signal from the previous display and provides the video signal to the next display; wherein at least one of the video display devices comprises a video relay circuit as above.
摘要翻译：提供一种视频中继电路，包括用于接收输入视频数据分组的输入通道; 第一电路，用于将输入视频数据分组转换为显示设备的数据; 第二电路，耦合到所述第一电路，以重新调整和重新驱动所述数据信道; 用于将视频数据分组耦合到输出流的输出通道。还提供了包括如上所述的视频中继电路和包括视频源的视频显示设备的菊花链的视频数据传输链路; 多个视频显示装置，其中第一视频显示装置耦合到视频数据源，并且每个另外的视频显示装置从前一个显示器接收源信号，并将视频信号提供给下一个显示; 其中至少一个视频显示装置包括如上所述的视频中继电路。

18. 发明授权

US5994918A Zero delay regenerative circuit for noise suppression on a computer data bus 失效
标题翻译：零延迟再生电路，用于计算机数据总线上的噪声抑制
公开(公告)号：US5994918A
公开(公告)日：1999-11-30
申请号：US924720
申请日：1997-08-29
申请人： Amitabh Mehra
发明人： Amitabh Mehra
IPC分类号： G06F13/40 , H04L25/24 , H03K19/003 , H03K19/00 , H03K19/0175
CPC分类号： G06F13/4077 , H04L25/247
摘要： A novel zero delay regenerative circuit is presented. The circuit, when connected to a data bus, suppresses noise, reduces time delay and provides sharper edge rates. A first input of a NOR gate is connected to an input node. A second input of the NOR gate is connected to the precharge clock of the bus. The output of the NOR gate is connected to the gate terminate of a field-effect transistor (FET). With the drain terminal connected to ground, the source terminal of the FET is connected to an output node. The input and output nodes are shorted together.
摘要翻译：提出了一种新颖的零延迟再生电路。当连接到数据总线时，该电路抑制噪声，减少时间延迟并提供更高的边沿速率。 NOR门的第一输入端连接到输入节点。 NOR门的第二个输入端连接到总线的预充电时钟。 NOR门的输出端连接到场效应晶体管（FET）的栅极端。漏极端子连接到地，FET的源极端子连接到输出节点。输入和输出节点一起短路。

19. 发明授权

US4412336A Storage comparator, for regenerating digital electric signals and digital transmission system using such a comparator 失效
标题翻译：存储比较器，用于再生数字电信号和使用这种比较器的数字传输系统
公开(公告)号：US4412336A
公开(公告)日：1983-10-25
申请号：US203380
申请日：1980-11-03
申请人： Michel Peltier , Maurice Gloanec , Gerard Nuzillat , Vincent Maurel , Michel Charrier
发明人： Michel Peltier , Maurice Gloanec , Gerard Nuzillat , Vincent Maurel , Michel Charrier
IPC分类号： H04L25/03 , H03K5/08 , H03K17/30 , H03K17/687 , H03K19/0952 , H04L25/24 , H04L25/52 , H04L25/66 , H03K5/153
CPC分类号： H04L25/247
摘要： Device for regenerating digital signals transmitted along a coaxial line.So as to transmit information at flow rates greater than or equal to 650 Mbauds, the storage comparator of the invention is constructed in the form of an integrated circuit on AsGa and with negative threshold voltage MESFET transistors. It comprises an adjustable threshold voltage comparator stage, a type-D flip-flop for storage and resynchronization with respect to an external clock, and an output matching stage which may provide summation at its output.
摘要翻译：用于再生沿着同轴线传输的数字信号的装置。为了以大于或等于650M波特的流速传输信息，本发明的存储比较器以AsGa上的集成电路和负阈值电压MESFET晶体管的形式构成。它包括一个可调节的阈值电压比较器级，一个D型触发器，用于存储和重新同步相对于一个外部时钟;一个输出匹配级可以在其输出端提供求和。

20. 发明授权

US2685646A Apparatus for reshaping electric pulses 失效
标题翻译：用于重塑电脉冲的装置
公开(公告)号：US2685646A
公开(公告)日：1954-08-03
申请号：US26161751
申请日：1951-12-14
申请人： GEN ELECTRIC CO LTD
发明人： WILLIAM WARD PETER
IPC分类号： H03K5/05 , H03K5/12 , H04J3/00 , H04L25/24
CPC分类号： H04L25/247 , H03K5/05 , H03K5/12 , H04J3/00

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