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11. 发明公开

EP1911163A1 SIGMA DELTA MODULATORS 有权
标题翻译： Σ-Δ调制
公开(公告)号：EP1911163A1
公开(公告)日：2008-04-16
申请号：EP06744355.6
申请日：2006-06-29
申请人： QUEEN MARY AND WESTFIELD COLLEGE
发明人： SANDLER, Mark Brian , REISS, Joshua Daniel
IPC分类号： H03M3/00 , H03M7/32 , H03M7/36
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
摘要： A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behaviour has been observed, and major changes to design are not normally required to implement the detection mechanism.

12. 发明专利

JP4796141B2 Sigma-delta modulator 有权
公开(公告)号：JP4796141B2
公开(公告)日：2011-10-19
申请号：JP2008522071
申请日：2006-06-29
申请人：クイーンマリーアンドウエストフィールドカレッジ, ユニバーシティーオブロンドン
发明人：マークブライアンサンドラー， , ジョシュアダニエルレイス，
IPC分类号： H03M3/02 , H03M3/00 , H03M7/00
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037

13. 发明申请

WO2007010298A1 SIGMA DELTA MODULATORS 审中-公开
标题翻译： SIGMA DELTA调制器
公开(公告)号：WO2007010298A1
公开(公告)日：2007-01-25
申请号：PCT/GB2006/050175
申请日：2006-06-29
申请人： QUEEN MARY & WESTFIELD COLLEGE , SANDLER, Mark Brian , REISS, Joshua Daniel
发明人： SANDLER, Mark Brian , REISS, Joshua Daniel
IPC分类号： H03M3/00 , H03M7/32 , H03M7/36
CPC分类号： H03M7/3011 , H03M3/362 , H03M3/422 , H03M3/438 , H03M7/3037
摘要： A method is provided for detecting limit cycles in a sigma delta modulator having an output signal that varies over a series of time intervals. In this method a first value that is indicative of the level of the modulator output signal after a predetermined time interval is stored in a first memory, and a second value that is indicative of the level of the modulator output signal after a further time interval subsequent to the predetermined time interval is stored in a second memory. The first value stored in the first memory is compared with the second value stored in the second memory, and an output indicative of a tendency for limit cycles to be produced in the modulator output signal is provided in response to such comparison. Such a method is particularly advantageous for detecting limit cycles in a sigma delta modulator as it can be implemented in a straightforward manner and offers a very accurate limit cycle detection mechanism. As a result it only becomes necessary to activate a limit cycle removal mechanism when limit cycle behaviour has been observed, and major changes to design are not normally required to implement the detection mechanism.
摘要翻译：提供了一种用于检测具有在一系列时间间隔上变化的输出信号的Σ-Δ调制器中的极限周期的方法。在该方法中，将指示预定时间间隔之后的调制器输出信号的电平的第一值存储在第一存储器中，以及指示后续时间间隔之后的调制器输出信号电平的第二值到预定时间间隔被存储在第二存储器中。存储在第一存储器中的第一值与存储在第二存储器中的第二值进行比较，并且响应于这种比较，提供表示在调制器输出信号中产生极限周期趋势的输出。这种方法对于在Σ-Δ调制器中检测极限循环特别有利，因为它可以以直接的方式实现并提供非常精确的极限循环检测机制。因此，仅当观察到极限循环行为时才需要激活极限循环去除机构，并且通常不需要对设计的主要改变来实现检测机制。

14. 发明申请

WO2004079915A2 FEEDBACK STEERING DELTA-SIGMA MODULATORS AND SYSTEMS USING THE SAME 审中-公开
标题翻译：反馈转向三角形调制器和使用它的系统
公开(公告)号：WO2004079915A2
公开(公告)日：2004-09-16
申请号：PCT/US2004/006881
申请日：2004-03-05
申请人： CIRRUS LOGIC, INC. , MELANSON, John, Laurence , FEI, Xiaofan , GABORIAU, Johann, G.
发明人： MELANSON, John, Laurence , FEI, Xiaofan , GABORIAU, Johann, G.
IPC分类号： H03M
CPC分类号： H03M7/3006 , H03M7/3011 , H03M7/3026 , H03M7/3033 , H03M7/3037
摘要： A digital to analog converter including an input for receiving an input signal, a ramp generator, and a delta-sigma modulator responsive to the input signal and an output of the ramp generator. An order of a noise shaping transfer function of the delta-sigma modulator is response to a level of the output of the ramp generator.
摘要翻译：数模转换器，包括用于接收输入信号的输入端，斜坡发生器和响应于输入信号和斜坡发生器输出的Δ-Σ调制器。 Δ-Σ调制器的噪声整形传递函数的顺序响应于斜坡发生器的输出电平。

15. 发明申请

WO2007067850A1 CENTERED-PULSE CONSECUTIVE EDGE MODULATION (CEM) METHOD AND APPARATUS 审中-公开
标题翻译：中心脉冲相关边缘调制（CEM）方法和装置
公开(公告)号：WO2007067850A1
公开(公告)日：2007-06-14
申请号：PCT/US2006/061103
申请日：2006-11-20
申请人： CIRRUS LOGIC, INC.
发明人： MELANSON, John, L. , HAGGE, MELVIN, L. , TROTTER, Briand, David
IPC分类号： H03M3/04 , H03M7/00
CPC分类号： H03M3/506 , H03M7/3026 , H03M7/3037
摘要： A consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta- sigma modulator.
摘要翻译：连续边缘调制（CEM）方法和装置提供脉冲输出，其有利地利用CEM的全边缘更新速率，同时提供基本居中的脉冲。该方法和装置也在输入控制路径中没有实质延迟的情况下运行。该装置包括接收了δ-Σ调制器量化器的输出的C-Σ后噪声整形调制器。在每个边缘处以极性交替施加非线性校正信号，并施加到量化器输入或被设计成量化器传递函数。非线性校正信号补偿噪声整形调制器输出，使得CEM输出脉冲的预期上升沿和下降沿宽度相对于Δ-Σ调制器的DC输入基本相等。

16. 发明申请

WO2004079915A3 FEEDBACK STEERING DELTA-SIGMA MODULATORS AND SYSTEMS USING THE SAME 审中-公开
标题翻译：反馈转向三角形调制器和使用它的系统
公开(公告)号：WO2004079915A3
公开(公告)日：2005-10-06
申请号：PCT/US2004006881
申请日：2004-03-05
申请人： CIRRUS LOGIC INC , MELANSON JOHN LAURENCE , FEI XIAOFAN , GABORIAU JOHANN G
发明人： MELANSON JOHN LAURENCE , FEI XIAOFAN , GABORIAU JOHANN G
IPC分类号： H03M20060101 , H03M3/00 , H03M7/32 , H03M7/34 , H03M7/36 , H03M7/38
CPC分类号： H03M7/3006 , H03M7/3011 , H03M7/3026 , H03M7/3033 , H03M7/3037
摘要： A digital to analog converter including an input for receiving an input signal, a ramp generator, and a delta-sigma modulator responsive to the input signal and an output of the ramp generator. An order of a noise shaping transfer function of the delta-sigma modulator is response to a level of the output of the ramp generator.
摘要翻译：数模转换器，包括用于接收输入信号的输入端，斜坡发生器和响应于输入信号和斜坡发生器输出的Δ-Σ调制器。 Δ-Σ调制器的噪声整形传递函数的顺序响应于斜坡发生器的输出电平。

17. 发明公开

EP1618667A1 SIGMA-DELTA MODULATOR 有权
标题翻译： Σ-Δ调制
公开(公告)号：EP1618667A1
公开(公告)日：2006-01-25
申请号：EP04725134.3
申请日：2004-04-13
申请人： Koninklijke Philips Electronics N.V.
发明人： JANSSEN, Erwin , REEFMAN, Derk
IPC分类号： H03M3/00
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M3/454 , H03M7/3028 , H03M7/3037 , H03M7/304
摘要： A sigma-delta modulator (SDM) including n (n≥1) integrators in series, where a first of the n integrators receiving an input signal, at least one Q device, which acts as a quantizer when an absolute value of a signal input thereto is smaller and as a gain element (either with or without offset) when the absolute value of the signal input thereto is larger, and a device for quantizing an output of the unit. The SDM may be a feed back or feed forward SDM. The SDM may include a single or multiple Q devices. The single Q device may be positioned so that the signal input to the one Q device is an output of the last integrator and the output of the one device Ql is input to the device for quantizing and/or to the n integrators. For multiple Q devices, each of the Q devices may have different parameters set to improve stability, improve SNR, and/or reduce introduction of artifacts. The SDM may be part of an analog to digital converter and/or a digital to digital converter. The SDM may process digital or analog signals, for example, a 1-bit signal.

18. 发明公开

EP1345375A2 Method and apparatus for frequency modulation 有权
标题翻译： Verfahren und Einrichtung zur Frequenzmodulation
公开(公告)号：EP1345375A2
公开(公告)日：2003-09-17
申请号：EP03005251.8
申请日：2003-03-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Adachi, Hisashi , Sakakura, Makoto
IPC分类号： H04L27/12
CPC分类号： H03C3/0966 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03L7/1976 , H03M7/3022 , H03M7/3037 , H03M7/304 , H04L27/12
摘要： A voltage controlled oscillator (1), a variable frequency divider (2), a phase comparator (3), and a loop filter (4) form a Phase Locked Loop (PLL). A sigma-delta modulator 5 sigma-delta modulates data obtained by adding a fractional part (M2) of the frequency division factor data with modulation data (X) by using an output signal of the variable frequency divider (2) as a clock. An output signal of the sigma-delta modulator (5) is added to an integral part (M1) of the frequency division factor data, and the resultant data becomes effective frequency division factor data (13) of the variable frequency divider (2). An output signal of the sigma-delta modulator (5) also becomes control data (14) after passing through a D/A converter (6), a low-pass filter (7), and an amplitude adjustment circuit (8). The control data (14) is inputted into a frequency modulation terminal of the voltage controlled oscillator (1). Therefore, it is possible to provide a frequency modulator that can use a reference signal source having no frequency modulation function, and perform modulation over a wide range of frequencies based on a digital modulation signal.
摘要翻译：压控振荡器（1），可变分频器（2），相位比较器（3）和环路滤波器（4）形成锁相环（PLL）。 Σ-Δ调制器5σ-Δ调制通过使用可变分频器（2）的输出信号作为时钟将分频因子数据的分数部分（M2）与调制数据（X）相加获得的数据。 Σ-Δ调制器（5）的输出信号被加到分频因子数据的整数部分（M1），并且所得数据成为可变分频器（2）的有效分频系数数据（13）。 Σ-Δ调制器（5）的输出信号在通过D / A转换器（6），低通滤波器（7）和振幅调整电路（8）之后也成为控制数据（14）。控制数据（14）被输入到压控振荡器（1）的调频端子。因此，可以提供一种可以使用不具有频率调制功能的参考信号源的频率调制器，并且可以基于数字调制信号在宽范围的频率上进行调制。

19. 发明公开

EP0180461A3 Improvements in or relating to digital to analogue converters 失效
标题翻译：数字或数字转换器的改进
公开(公告)号：EP0180461A3
公开(公告)日：1989-03-29
申请号：EP85307833.5
申请日：1985-10-29
申请人： PLESSEY OVERSEAS LIMITED
发明人： Jackson, Thomas
IPC分类号： H03M1/86
CPC分类号： H03M7/3037 , H03M7/3028
摘要： An interpolating digital to analogue converter 2 comprises a combiner 4 for receiving a digital input signal. The output signal of the combiner is fed via a digital controller 6 to one step quantiser 8. The output signal of the one step quantiser 8 is fed via a feedback loop 10 to the combiner 4, where it is combined with the digital input signal, and also to an analogue filter to provide a voltage output which is proportional to the digital input signal. The digital controller 6 may comprise an optimum controller, such as a type 1, type 2 or type 3 controller, and is chosen according to the resolution required.
摘要翻译：内插数模转换器2包括用于接收数字输入信号的组合器4。组合器的输出信号通过数字控制器6馈送到一步量化器8.一步量化器8的输出信号通过反馈环路10馈送到组合器4，在组合器4中与数字输入信号进行组合，并且还提供到模拟滤波器以提供与数字输入信号成比例的电压输出。数字控制器6可以包括最佳控制器，例如类型1，类型2或类型3控制器，并且根据所要求的分辨率来选择。

20. 发明授权

EP1618667B1 SIGMA-DELTA MODULATOR 有权
标题翻译： SIGMA-DELTA调制器
公开(公告)号：EP1618667B1
公开(公告)日：2007-05-30
申请号：EP04725134.3
申请日：2004-04-13
申请人： Koninklijke Philips Electronics N.V.
发明人： JANSSEN, Erwin , REEFMAN, Derk
IPC分类号： H03M3/00
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M3/454 , H03M7/3028 , H03M7/3037 , H03M7/304
摘要： A sigma-delta modulator (SDM) including n (n≥1) integrators in series, where a first of the n integrators receiving an input signal, at least one Q device, which acts as a quantizer when an absolute value of a signal input thereto is smaller and as a gain element (either with or without offset) when the absolute value of the signal input thereto is larger, and a device for quantizing an output of the unit. The SDM may be a feed back or feed forward SDM. The SDM may include a single or multiple Q devices. The single Q device may be positioned so that the signal input to the one Q device is an output of the last integrator and the output of the one device Ql is input to the device for quantizing and/or to the n integrators. For multiple Q devices, each of the Q devices may have different parameters set to improve stability, improve SNR, and/or reduce introduction of artifacts. The SDM may be part of an analog to digital converter and/or a digital to digital converter. The SDM may process digital or analog signals, for example, a 1-bit signal.

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