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11. 发明专利

JP5788001B2 二軸異方性を有する磁気トンネリング接合素子の提供方法及びシステム有权
标题翻译：它提供了双轴各向异性为磁性隧道结装置的方法和系统
公开(公告)号：JP5788001B2
公开(公告)日：2015-09-30
申请号：JP2013524092
申请日：2011-07-28
申请人：グランディスインコーポレイテッド , GRANDIS,INC.
发明人：ドミトロ・アパルコフ
IPC分类号： H01L27/105 , H01L43/08 , H01L21/8246
CPC分类号： H01L43/08 , B82Y25/00 , H01F10/3254 , H01F10/3286 , H01F10/3295

12. 发明专利

JP5787972B2 逆デュアル磁気トンネル接合要素を提供するための方法およびシステム有权
标题翻译：方法和系统，用于提供反向双磁性隧道结元件
公开(公告)号：JP5787972B2
公开(公告)日：2015-09-30
申请号：JP2013500115
申请日：2011-03-13
申请人：グランディスインコーポレイテッド , GRANDIS,INC.
发明人：シュエティ・タン , ジン・ウ
IPC分类号： H01L27/105 , H01L29/82 , H01L43/08 , H01L21/8246
CPC分类号： G11C11/1675 , G11C11/16 , H01L43/12

13. 发明专利

JP2012104825A Method and system for providing hybrid magnetic tunneling junction element with improved switching 有权
标题翻译：用于提供具有改进的开关的混合磁性隧道结构元件的方法和系统
公开(公告)号：JP2012104825A
公开(公告)日：2012-05-31
申请号：JP2011242355
申请日：2011-11-04
申请人： Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： DMYTRO APALKOV , MOHAMMED TAWFIK CRAWNBI
IPC分类号： H01L27/105 , H01L21/8246 , H01L29/82 , H01L43/08
CPC分类号： G11C11/1675 , G11C11/161
摘要： PROBLEM TO BE SOLVED: To provide a method and system for providing a hybrid magnetic tunneling junction element with improved switching.SOLUTION: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
摘要翻译：要解决的问题：提供一种用于提供具有改进的切换的混合磁隧道结元件的方法和系统。
解决方案：描述了一种用于提供可用于磁性装置中的磁结的方法和系统。磁结包括钉扎层，非磁性间隔层和自由层。非磁性间隔层位于被钉扎层和自由层之间。自由层具有容易的锥形磁各向异性。磁结被配置为使得当写入电流通过磁结时，自由层可在多个稳定磁状态之间切换。版权所有（C）2012，JPO＆INPIT

14. 发明专利

JP2009266861A Magnetic storage element and magnetic storage device 有权
标题翻译：磁存储元件和磁存储器件
公开(公告)号：JP2009266861A
公开(公告)日：2009-11-12
申请号：JP2008111080
申请日：2008-04-22
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： TAKADA YUTAKA , OSANAGA TAKASHI , KUROIWA TAKEHARU , FURUKAWA TAISUKE
IPC分类号： H01L43/08 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/228 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a magnetic storage element having a low rewriting current and sufficient magnetic characteristics in a magnetic storage device of a magnetization inversion type by spin implantation.
SOLUTION: A magnetic resistance element is a multilayer structure of a fixing layer (PL) with a magnetization direction fixed to a constant direction, a non-magnetic dielectric layer (TN1) brought into contact with the fixing layer (PL), and a storage layer (FL) having a first surface brought into contact with the non-magnetic dielectric layer (TN1) and a second surface confronted with the first surface. In this resistance element inverting the magnetization direction of the storage layer (FL) by current flowing in the multilayer structure, the whole first surface of the storage layer (FL) is covered with the non-magnetic dielectric layer (TN1) and the first surface of the non-magnetic dielectric layer (TN1) is exposed to surround a junction surface in the junction surface of the non-magnetic dielectric layer (TN1) and the fixing layer (PL).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过旋转植入在磁化反转型的磁存储装置中提供具有低重写电流和足够的磁特性的磁存储元件。解决方案：磁阻元件是固定层（PL）的多层结构，其磁化方向固定在恒定方向，非磁性介电层（TN1）与定影层（PL）接触，以及具有与非磁性介电层（TN1）接触的第一表面和与第一表面相对的第二表面的存储层（FL）。在该电阻元件中，通过在多层结构中流动的电流使存储层（FL）的磁化方向反转，存储层（FL）的整个第一表面被非磁性介电层（TN1）覆盖，第一表面的非磁性介电层（TN1）暴露于非磁性介电层（TN1）和固定层（PL）的接合面的接合面。版权所有（C）2010，JPO＆INPIT

15. 发明专利

JP2008097665A Sense amplifier circuit 审中-公开
标题翻译：感应放大器电路
公开(公告)号：JP2008097665A
公开(公告)日：2008-04-24
申请号：JP2006275414
申请日：2006-10-06
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To reduce erroneous writing when reading data in a memory. SOLUTION: The sense amplifier circuit 10 reads data from the STT-MRAM storing the data through read lines LIOFx and LIOBx (x= 1, 0) to the magnetoresistive elements connected to bit lines BLxx (xx= 00, 01, 10, 11, ..., M0, M1) and word lines WLy (y= 0, 1, ..., 2n, 2n+1). When reading the data, it controls the bias voltages Vbias to apply to the magnetoresistive elements by changing them depending on their resistances. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少在存储器中读取数据时的错误写入。解决方案：读出放大器电路10通过读线LIOFx和LIOBx（x = 1,0）从存储数据的STT-MRAM读取连接到位线BLxx（xx = 00,01,10）的磁阻元件的数据，11，...，M0，M1）和字线WLy（y = 0,1，...，2n，2n + 1）。当读取数据时，它通过根据其电阻改变来控制偏置电压Vbias以应用于磁阻元件。版权所有（C）2008，JPO＆INPIT

16. 发明专利

JP2012235159A Manufacturing method for magnetic memory device and magnetic memory device 有权
标题翻译：磁记忆装置和磁记忆装置的制造方法
公开(公告)号：JP2012235159A
公开(公告)日：2012-11-29
申请号：JP2012169160
申请日：2012-07-31
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社 , Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： FURUTA HARUO , UENO SHUICHI , MATSUDA AKIFUMI , FUKUMURA TATSUYA , KUROIWA TAKEHARU , WANG LIEN-CHANG , CHEN EUGENE , HUAI YIMING
IPC分类号： H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a nonvolatile magnetic memory which reduces dispersion of characteristics between TMR elements and has high manufacturing yield, and to provide structure of the nonvolatile magnetic memory.SOLUTION: A manufacturing method for a magnetic memory device having a TMR element comprises: a step for forming an insulating film on an interlayer insulating film where a wiring layer is disposed; an opening step for forming an opening on the insulating film so as to expose the wiring layer; a metal layer forming step for forming a metal layer on the insulating film so as to fill the opening with the metal layer; a CMP step for grinding to remove the metal layer on the insulating film by using a CMP method and making the metal layer remaining in the opening to be a lower electrode; and a step for forming the TMR element on the lower electrode.
摘要翻译：解决的问题：提供一种减少TMR元件之间的特性分散并且制造成品率高的非易失性磁性存储器的制造方法，提供非易失性磁性存储器的结构。解决方案：具有TMR元件的磁存储器件的制造方法包括：在布置有布线层的层间绝缘膜上形成绝缘膜的步骤; 用于在所述绝缘膜上形成开口以使所述布线层露出的开口步骤; 金属层形成步骤，用于在绝缘膜上形成金属层，以便用金属层填充开口; CMP步骤，通过使用CMP方法研磨以除去绝缘膜上的金属层，并使残留在开口中的金属层成为下电极; 以及在下电极上形成TMR元件的步骤。版权所有（C）2013，JPO＆INPIT

17. 发明专利

JP2012109010A MEMORY WRITING ERROR CORRECTION CIRCUIT 审中-公开
公开(公告)号：JP2012109010A
公开(公告)日：2012-06-07
申请号：JP2011251457
申请日：2011-11-17
申请人： GRANDIS INC
发明人： ADRIAN E ONG , VLADIMIR NIKITIN
IPC分类号： G11C29/44 , G11C11/15 , G11C29/12
摘要： PROBLEM TO BE SOLVED: To provide a memory writing error correction circuit.SOLUTION: A memory circuit includes an address designation circuit for receiving the addresses of an array, a row decoder, a column decoder and a data bit, a control logic for receiving a command and transmitting a control signal to a memory system block, and a detecting and writing driver circuit connected to a selected column. A concealment and reading comparison circuit is connected between the detection circuit and the writing driver, and connects an error flag to the control logic circuit in response to comparison between a data bit in an input latch and a data out read from the memory array. A writing error address tag memory is connected to the address designation circuit through a bidirectional bus in response to the error flag. A data input and output circuit having a first bidirectional bus and a second bidirectional bus for transmitting and receiving the data bit is provided. The writing error address tag memory stores an address when the error flag is set, and provides the address during a rewriting operation.

18. 发明专利

JP2012084218A Pseudo page mode memory architecture and method 有权
标题翻译： PSEUDO页面模式存储器架构和方法
公开(公告)号：JP2012084218A
公开(公告)日：2012-04-26
申请号：JP2011224001
申请日：2011-10-11
申请人： Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： ADRIAN E ONG
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： PROBLEM TO BE SOLVED: To provide an MRAM which provides cost advantage of a DRAM, high-speed read-write performance of an SRAM, and nonvolatility of a flash memory.SOLUTION: A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.
摘要翻译：要解决的问题：提供提供DRAM的成本优势，SRAM的高速读写性能和闪速存储器的非易失性的MRAM。解决方案：非易失性存储器阵列包括多个字线和多个列。其中一列还包括耦合到第一，第二，第三和第四信号线的双稳态再生电路。该列还包括具有耦合到第一和第二信号线的载流端子和耦合到多个字线之一的控制端子的非易失性存储单元。该列还包括第一晶体管和第二晶体管。第一晶体管耦合到双稳态再生电路的第一端子和第五信号线。第二晶体管具有耦合到双稳态再生电路的第二端子的第一载流端子和耦合到第六信号线的第二载流端子。第一和第二晶体管的栅极端子耦合到第七信号线。版权所有（C）2012，JPO＆INPIT

19. 发明专利

JP2009043831A Magnetic memory device and its manufacturing method 有权
标题翻译：磁记忆装置及其制造方法
公开(公告)号：JP2009043831A
公开(公告)日：2009-02-26
申请号：JP2007205516
申请日：2007-08-07
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： UENO SHUICHI , FURUTA HARUO , MATSUDA AKIFUMI , FUKUMURA TATSUYA , HASEGAWA SHIN , HIRANO SHINYA , CHIBAHARA HIROYUKI , OSHITA HIROSHI
IPC分类号： H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory device capable of reducing fluctuation in a write current of a TMR element, highly reliable and capable of being downsized.
SOLUTION: This manufacturing method of the magnetic memory device including the TMR element includes a step of forming a lower wiring layer, a step of forming an interlayer insulation layer on the lower wiring layer, a step of forming an aperture to expose the lower wiring layer on the interlayer insulation layer, a step of forming a barrier metal layer to cover the internal surfaces of the interlayer insulation layer and the aperture, a step of forming a metallic layer on the barrier metal layer to bury the aperture, a step of grinding off the metallic layer on the barrier metal layer using the barrier metal layer as a stopper to form a wiring layer including the metallic layer buried in the aperture and the barrier metal layer, and an element preparation step of forming the TMR element on the wiring layer.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够减少TMR元件的写入电流的波动的磁存储器件，高度可靠并且能够被小型化。解决方案：包括TMR元件的磁存储器件的制造方法包括形成下布线层的步骤，在下布线层上形成层间绝缘层的步骤，形成孔以暴露层间绝缘层上的下布线层，形成阻挡金属层以覆盖层间绝缘层和孔的内表面的步骤，在阻挡金属层上形成金属层以埋入孔的步骤，将步骤使用阻挡金属层作为阻挡层研磨阻挡金属层上的金属层，以形成包含埋在孔中的金属层和阻挡金属层的布线层，以及将元件制备步骤在接线层。版权所有（C）2009，JPO＆INPIT

20. 发明专利

JP2008135433A Magnetic storage 审中-公开
标题翻译：磁性存储
公开(公告)号：JP2008135433A
公开(公告)日：2008-06-12
申请号：JP2006318295
申请日：2006-11-27
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a magnetic storage having a folded structure enabling satisfactory rewrite without increasing the area of a memory cell.
SOLUTION: The memory cell of the magnetic storage includes: a source region; a nearly rectangular active region containing first and second drain regions provided at both the sides of the source region while a channel region is sandwiched; two word lines provided along the channel region; a first bit line provided on the active region in a direction vertical to the word line; a source contact provided at an opposite side while the first bit line is sandwiched, and first and second drain contacts; a source line connected to the source contact and provided in parallel with the first bit line; a second bit line provided in parallel with the first bit line while the first and second drain contacts are sandwiched; and first and second TMR elements provided between the first bit line and the first drain contact, and between the second bit line and the second drain contact, respectively.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有能够令人满意地重写而不增加存储单元的面积的折叠结构的磁存储器。解决方案：磁存储器的存储单元包括：源区; 近似矩形的有源区域，其包含设置在源极区域的两侧的第一和第二漏极区域，同时夹着沟道区域; 沿通道区域设置两条字线; 在与所述字线垂直的方向上设置在所述有源区上的第一位线; 在第一位线被夹持的同时设置在相对侧的源极触点，以及第一和第二漏极触点; 源极线，连接到源极触点并与第一位线并联; 与第一位线并联设置的第二位线，同时第一和第二漏极接触件被夹持; 以及分别设置在第一位线和第一漏极接触之间以及第二位线和第二漏极接触之间的第一和第二TMR元件。版权所有（C）2008，JPO＆INPIT

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