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1. 发明专利

JP2012084218A Pseudo page mode memory architecture and method 有权
标题翻译： PSEUDO页面模式存储器架构和方法
公开(公告)号：JP2012084218A
公开(公告)日：2012-04-26
申请号：JP2011224001
申请日：2011-10-11
申请人： Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： ADRIAN E ONG
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： PROBLEM TO BE SOLVED: To provide an MRAM which provides cost advantage of a DRAM, high-speed read-write performance of an SRAM, and nonvolatility of a flash memory.SOLUTION: A non-volatile memory array includes a plurality of word-lines and a plurality of columns. One of the columns further includes a bistable regenerative circuit coupled to a first, a second, a third, and a fourth signal lines. The column also includes a non-volatile memory cell having current carrying terminals coupled to the first and second signal lines and a control terminal coupled to one of the plurality of word-lines. The column further includes a first transistor and a second transistor. The first transistor is coupled to the first terminal of the bistable regenerative circuit, and to a fifth signal line. The second transistor has a first current carrying terminal coupled to the second terminal of the bistable regenerative circuit, and a second current carrying terminal coupled to a sixth signal line. The gate terminals of the first and second transistors are coupled to a seventh signal line.
摘要翻译：要解决的问题：提供提供DRAM的成本优势，SRAM的高速读写性能和闪速存储器的非易失性的MRAM。解决方案：非易失性存储器阵列包括多个字线和多个列。其中一列还包括耦合到第一，第二，第三和第四信号线的双稳态再生电路。该列还包括具有耦合到第一和第二信号线的载流端子和耦合到多个字线之一的控制端子的非易失性存储单元。该列还包括第一晶体管和第二晶体管。第一晶体管耦合到双稳态再生电路的第一端子和第五信号线。第二晶体管具有耦合到双稳态再生电路的第二端子的第一载流端子和耦合到第六信号线的第二载流端子。第一和第二晶体管的栅极端子耦合到第七信号线。版权所有（C）2012，JPO＆INPIT

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