专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2008218649A Semiconductor device, manufacturing method thereof, and magnetic memory element 审中-公开
标题翻译：半导体器件及其制造方法及磁记忆元件
公开(公告)号：JP2008218649A
公开(公告)日：2008-09-18
申请号：JP2007052952
申请日：2007-03-02
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KOGA TAKESHI , UENO SHUICHI , HIDAKA HIDETO , KAWAGOE TOMOYA
IPC分类号： H01L21/8246 , G11C11/15 , H01L27/10 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein it can utilize effectively the individual characteristics of different kinds of magnetic memory elements, and also provide magnetic memory elements having various element characteristics.
SOLUTION: The semiconductor device has a standard MRAM having magnetic tunnel junctions TMR including free layers MF wherein the magnetizing direction of each free layer MF is controlled by the magnetic field generated by the current flowing in the vicinity of each TMR, and has an STT-MRAM having TMRs including free layers MF wherein the magnetizing direction of each free layer MF is controlled by a spin injecting current fed to each TMR. Further, the standard MRAM and STT-MRAM are mounted on a single substrate.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件及其制造方法，其可以有效地利用不同种类的磁存储元件的各个特性，并且还提供具有各种元件特性的磁存储元件。解决方案：半导体器件具有包括自由层MF的磁隧道结TMR的标准MRAM，其中每个自由层MF的磁化方向由在每个TMR附近流动的电流产生的磁场控制，并且具有具有包括自由层MF的TMR的STT-MRAM，其中每个自由层MF的磁化方向由馈送到每个TMR的自旋注入电流控制。此外，标准MRAM和STT-MRAM安装在单个基板上。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008211011A Magnetic memory device and manufacturing method therefor 有权
标题翻译：磁记忆体装置及其制造方法
公开(公告)号：JP2008211011A
公开(公告)日：2008-09-11
申请号：JP2007046776
申请日：2007-02-27
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： FURUTA HARUO , UENO SHUICHI , MATSUDA AKIFUMI , FUKUMURA TATSUYA , KUROIWA TAKEHARU , WANG LIEN-CHANG , CHEN EUGENE , HUAI YIMING
IPC分类号： H01L21/8246 , H01L27/105 , H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a nonvolatile magnetic memory which reduces characteristic irregularities between TMR elements and offer high manufacturing yield, and to provide the structure of the nonvolatile magnetic memory.
SOLUTION: The manufacturing method for the magnetic memory device having a TMR element includes a step of forming an insulating film on an interlayer insulating film incorporating a wiring layer therein, an opening step of forming an opening on the insulating film to expose the wiring layer, a metal layer forming step of forming a metal layer on the insulating layer to fill the opening with the metal layer, a CMP step of grinding to remove the metal layer on the insulating layer using a CMP method and making the metal layer remaining in the opening into a lower electrode, and a step of forming the TMR element on the lower electrode.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种降低TMR元件之间的特征不均匀性并提供高制造成品率的非易失性磁存储器的制造方法，并提供非易失性磁存储器的结构。解决方案：具有TMR元件的磁存储器件的制造方法包括在其中包含布线层的层间绝缘膜上形成绝缘膜的步骤，在绝缘膜上形成开口以暴露出绝缘膜的步骤布线层，金属层形成步骤，在绝缘层上形成金属层以用金属层填充开口; CMP步骤，使用CMP方法研磨以去除绝缘层上的金属层，并使金属层保持在下部电极的开口中，以及在下部电极上形成TMR元件的步骤。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2008112525A Semiconductor storage 审中-公开
标题翻译：半导体存储
公开(公告)号：JP2008112525A
公开(公告)日：2008-05-15
申请号：JP2006295788
申请日：2006-10-31
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To reduce the occurrence of write error when reading data from a memory device.
SOLUTION: The semiconductor storage comprises: a memory cell array 4; a R/W control circuit 5; and a reference resistance circuit. The memory cell array 4 stores and holds data in a plurality of magnetoresistive elements connected to a word line WLy (y=0, 1, ..., 2n, 2n+1, ...), and a bit line BLix, and a source line SLix (i=0, 1, ..., m, ..., M; x=0, 1). The R/W control circuit 5 controls voltage applied to the bit line BLix and source line SLix. The reference resistance circuit generates a prescribed reference resistance value. The R/W control circuit 5 performs control so that voltages Vout_B0, Vout_B1 applied to the reference resistance circuit are increased when the value of resistance in the magnetoresistive element is the maximum resistance value Rmax when reading data from the memory cell array 4, and reduces voltages Vout0, Vout1 applied to the magnetoresistive element.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少从存储器件读取数据时写入错误的发生。解决方案：半导体存储器包括：存储单元阵列4; R / W控制电路5; 和参考电阻电路。存储单元阵列4存储并保持连接到字线WLy（y = 0,1，...，2n，2n + 1，...）和位线BLix的多个磁阻元件中的数据，以及源线SLix（i = 0,1，...，m，...，M; x = 0,1）。 R / W控制电路5控制施加到位线BLix和源极线SLix的电压。参考电阻电路产生规定的参考电阻值。 R / W控制电路5进行控制，使得当从存储单元阵列4读取数据时，当磁阻元件的电阻值为最大电阻值Rmax时，施加到参考电阻电路的电压Vout_B0，Vout_B1增加，并且减小施加到磁阻元件的电压Vout0，Vout1。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2012119715A Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization 有权
标题翻译：具有高度均匀性和平面平衡磁化的自由层的旋转传递元件
公开(公告)号：JP2012119715A
公开(公告)日：2012-06-21
申请号：JP2012022427
申请日：2012-02-03
申请人： Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： NGUYEN PAUL P , YIMING HUAI
IPC分类号： H01L27/105 , G11C11/16 , G11C17/02 , H01F10/30 , H01F10/32 , H01F41/30 , H01L21/8246 , H01L29/82 , H01L31/119 , H01L43/00 , H01L43/08 , H01L43/12
CPC分类号： H01F41/302 , B82Y25/00 , B82Y40/00 , G01R33/093 , G01R33/1284 , G11C11/161 , G11C11/1675 , H01F10/30 , H01F10/3236 , H01F10/3263 , H01F10/3272 , H01F10/3286 , H01L43/08 , Y10T428/26 , Y10T428/261 , Y10T428/265
摘要： PROBLEM TO BE SOLVED: To provide a method and system for manufacturing a magnetic element that can be used in a magnetic memory.SOLUTION: The magnetic element includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The spacer layer resides between the pinned layer and the free layer. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The magnetic element further can include a barrier layer and a second pinned layer. As another option, the magnetic element includes a second pinned layer, a second spacer layer, and a second free layer magnetostatically coupled to the free layer. At least one free layer has a high perpendicular anisotropy. The high perpendicular anisotropy has perpendicular anisotropy energy which is at least twenty percent and less than one hundred percent of the out-of-plane demagnetization energy.
摘要翻译：要解决的问题：提供一种可用于磁存储器中的用于制造磁性元件的方法和系统。解决方案：磁性元件包括钉扎层，非磁性间隔层和自由层。间隔层位于被钉扎层和自由层之间。当写入电流通过磁性元件时，可以使用自旋转移来切换自由层。磁性元件还可以包括阻挡层和第二固定层。作为另一选择，磁性元件包括第二固定层，第二间隔层和静电耦合到自由层的第二自由层。至少一个自由层具有高的垂直各向异性。高垂直各向异性具有垂直各向异性能，其至少为面外退磁能的百分之二十且小于百分之一百。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012104848A Spin transition magnetic element having low saturation magnetization free layer 有权
标题翻译：具有低饱和磁化自由层的旋转磁化元件
公开(公告)号：JP2012104848A
公开(公告)日：2012-05-31
申请号：JP2011286885
申请日：2011-12-27
申请人： Grandis Inc , グランディスインコーポレイテッドGrandis,Inc.
发明人： NGUYEN PAUL P , YIMING HUAI , DIAO ZUTAO , ALBERT FRANK
IPC分类号： H01L27/105 , G11C11/15 , G11C11/16 , H01F10/16 , H01F10/32 , H01F41/30 , H01H9/00 , H01L21/8246 , H01L29/82 , H01L43/08 , H01L43/10
CPC分类号： H01L43/10 , B82Y25/00 , B82Y40/00 , G11C11/161 , H01F10/16 , H01F10/3263 , H01F10/3272 , H01F41/303
摘要： PROBLEM TO BE SOLVED: To perform writing in a magnetic element with a lower switching current density.SOLUTION: A magnetic element 100 includes a fixed layer 110, a nonmagnetic spacer layer 120, and a free layer 130 having free layer magnetization. The spacer layer 120 exists between the fixed layer 110 and the free layer 130. The free layer 130 contains a doped ferromagnetic material. The doped ferromagnetic material contains at least one ferromagnetic material diluted by at least one non-magnetic material so that the free layer 130 has low saturation magnetization of 1430 emu/cmor less at room temperature, at least one ferromagnetic material doped ferrimagnetically, or at least one ferromagnetic material diluted by at least one non-magnetic material and doped ferrimagnetically. When a write current passes through the magnetic element 100, free layer magnetization is switched using spin transition.
摘要翻译：要解决的问题：在具有较低开关电流密度的磁性元件中执行写入。解决方案：磁性元件100包括固定层110，非磁性间隔层120和具有自由层磁化的自由层130。间隔层120存在于固定层110和自由层130之间。自由层130含有掺杂的铁磁材料。掺杂的铁磁材料包含至少一种由至少一种非磁性材料稀释的铁磁材料，使得自由层130具有低的饱和磁化强度（1430emu / cm 3以下）或至少一种由至少一种非磁性材料稀释的铁磁性材料，并且以铁磁性方式掺杂。当写入电流通过磁性元件100时，使用自旋跃迁来切换自由层的磁化。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2008112524A Semiconductor storage 审中-公开
标题翻译：半导体存储
公开(公告)号：JP2008112524A
公开(公告)日：2008-05-15
申请号：JP2006295780
申请日：2006-10-31
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To improve read precision without increasing a layout area.
SOLUTION: A semiconductor storage comprises: a memory cell array 4; a sense amplifier circuit 10; and a constant current source CCS. The memory cell array 4 stores and holds data on a plurality of resistor memory elements Rix (i=0, 1, ..., m, ..., M; x=0, 1) connected to a bit line BLix (i=0, 1, ..., m, ..., M; x=0, 1) and a source line SLix (i=0, 1, ..., m, ..., M; x=0, 1) respectively. The sense amplifier circuit 10 is used to read data from the memory cell array 4 via read lines LIOFx, LIOBx (x=0, 1). The constant current source CCS supplies a constant current Iconst to the bit line BLix (i=0, 1, ..., m, ..., M; x=0, 1) when reading data.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提高读取精度，而不增加布局面积。解决方案：半导体存储器包括：存储单元阵列4; 读出放大器电路10; 和恒流源CCS。存储单元阵列4存储和保存连接到位线BLix（i）的多个电阻器存储元件Rix（i = 0,1，...，m，...，M; x = 0,1）上的数据 = 0，1，...，m，...，M; x = 0,1）和源极线SLix（i = 0,1，...，m，...，M; x = 0 ，1）。读出放大器电路10用于经由读取行LIOFx，LIOBx（x = 0,1）从存储单元阵列4读取数据。当读数据时，恒流源CCS向位线BLix（i = 0,1，...，m，...，M; x = 0,1）提供恒定电流Iconst。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008258362A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008258362A
公开(公告)日：2008-10-23
申请号：JP2007098265
申请日：2007-04-04
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： H01L21/8246 , G11C11/15 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a small semiconductor memory device by reducing the size of a cell transistor by reducing switching current.
SOLUTION: A semiconductor memory device having a memory cell array containing a plurality of magnetoresistive elements R01 and a plurality of switching elements comprises a digit line DL00 or the like. The plurality of magnetoresistive elements are connected to a source line SL00 and a bit line BL00 arranged substantially in parallel with each other. Data are written in the magnetoresistive element by an STT (Spin Torque Transfer) writing method. The plurality of switching elements are connected to the plurality of magnetoresistive elements in series, respectively. The plurality of switching elements are controlled by a word line WL4n arranged substantially vertically relative to the source line and the bit line. A digit line is adjacent to the magnetoresistive element so that a predetermined magnetic field is generated relative to the magnetoresistive element. The digit line is arranged substantially in parallel with the source line.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过降低开关电流来减小单元晶体管的尺寸来提供小型半导体存储器件。解决方案：具有包含多个磁阻元件R01和多个开关元件的存储单元阵列的半导体存储器件包括数字线DL00等。多个磁阻元件连接到基本上彼此平行布置的源极线SL00和位线BL00。通过STT（自旋转矩转移）写入方式将数据写入磁阻元件。多个开关元件分别连接到多个磁阻元件。多个开关元件由相对于源极线和位线基本垂直布置的字线WL4n控制。数字线与磁阻元件相邻，从而相对于磁阻元件产生预定的磁场。数字线基本上与源极线平行地布置。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008135119A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2008135119A
公开(公告)日：2008-06-12
申请号：JP2006320520
申请日：2006-11-28
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of extending an output voltage range without deteriorating characteristics of a sense amplifier circuit.
SOLUTION: The semiconductor memory device is equipped with: a plurality of magneto-resistance elements Rx0, Rx1 respectively connected to bit lines BLx0, BLx1; a plurality of reference resistors Rmin, Rmax respectively connected to bit lines BL_Bx0, BL_Bx1; and the sense amplifier circuit 10. The magneto-resistance elements Rx0, Rx1 accumulate binary data. The reference resistors Rmin, Rmax are used for generating a reference resistance value Rref. The sense amplifier 10 includes N type transistors 28a-31a, 28b-31b which respectively make currents IA-ID flowing on each bit line to branch when the data are read out from the magneto-resistance elements Rx0, Rx1, and join respective branched currents with a current flowing on the corresponding bit line different from the bit lines whereon respective branched currents flow.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供能够延长输出电压范围而不劣化读出放大器电路的特性的半导体存储器件。解决方案：半导体存储器件配备有分别连接到位线BLx0，BLx1的多个磁阻元件Rx0，Rx1; 分别连接到位线BL_Bx0，BL_Bx1的多个参考电阻器Rmin，Rmax; 和读出放大器电路10.磁阻元件Rx0，Rx1累积二进制数据。参考电阻Rmin，Rmax用于产生参考电阻值Rref。读出放大器10包括N型晶体管28a-31a，28b-31b，它们在从磁阻元件Rx0，Rx1读出数据时分别使每个位线上流动的电流IA-ID分支，并连接相应的分支电流电流流过不同于相应分支电流流动的位线的相应位线。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2008097666A Driver circuit and semiconductor memory incorporating it 审中-公开
标题翻译：驱动电路和半导体存储器
公开(公告)号：JP2008097666A
公开(公告)日：2008-04-24
申请号：JP2006275415
申请日：2006-10-06
申请人： Grandis Inc , Renesas Technology Corp , グランディスインコーポレイテッドGrandis,Inc. , 株式会社ルネサステクノロジ
发明人： KAWAGOE TOMOYA
IPC分类号： G11C11/15
摘要： PROBLEM TO BE SOLVED: To secure a sufficient writing period when writing data and to reduce erroneous writing when reading data without particularly controlling the timing.
SOLUTION: This driver circuit for a semiconductor memory having magnetoresistive elements connected to bit lines BLix (i= 0, 1, ..., m, ..., M; x=0, 1) has a logic circuit to make predetermined logic calculations for the voltages on the row select line CSL and data writing control lines BFPx, BFNx (x=0, 1) and to output a pair of control circuits showing this logic calculation result, and a P-type transistor P1 and an N-type transistor N1 connected in series between the power source voltage VDD2 and the ground voltage Vgnd and to generate the control voltages of the bit line BLix (i= 0, 1, ..., m, ..., M; x=0, 1) based on the pair of control signals from the logic circuit.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在写入数据时确保足够的写入周期，并且在不特别控制定时的情况下读取数据时减少错误写入。解决方案：具有连接到位线BLix（i = 0,1，...，m，...，M; x = 0,1）的磁阻元件的半导体存储器的该驱动电路具有逻辑电路对行选择线CSL和数据写入控制线BFPx，BFNx（x = 0,1）上的电压进行预定的逻辑计算，并输出显示该逻辑计算结果的一对控制电路，以及P型晶体管P1和串联连接在电源电压VDD2和接地电压Vgnd之间的N型晶体管N1，并产生位线BLix（i = 0,1，...，m，...，M; x = 0,1），基于来自逻辑电路的一对控制信号。版权所有（C）2008，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式