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11. 发明申请

US20050222816A1 Compactor independent fault diagnosis 有权
标题翻译：压实机独立故障诊断
公开(公告)号：US20050222816A1
公开(公告)日：2005-10-06
申请号：US10925230
申请日：2004-08-23
申请人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
发明人： Wu-Tung Cheng , Kun-Han Tsai , Yu Huang , Nagesh Tamarapalli , Janusz Rajski
IPC分类号： G06F11/30 , G06F15/00
CPC分类号： G01R31/318547 , G06F11/267
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test is received. A transformation function performed by the compactor to the test responses captured in the circuit-under-test is determined. A diagnostic procedure for evaluating uncompressed test responses is modified into a modified diagnostic procedure that incorporates the transformation function therein. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media comprising lists of fault candidates identified by any of the disclosed methods or circuit descriptions created or modified by the disclosed methods are provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在某些公开的实施例中，提供了用于从压缩测试响应诊断故障的方法。例如，在一个示例性实施例中，接收至少部分基于扫描的测试电路和压实器的电路描述，用于压缩在待测电路中捕获的测试响应。确定由压实机对被测电路中捕获的测试响应执行的变换功能。用于评估未压缩测试响应的诊断程序被修改为并入其中的变换功能的修改的诊断过程。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样地，提供了包括通过由所公开的方法创建或修改的任何公开的方法或电路描述所识别的故障候选列表的计算机可读介质。

12. 发明申请

US20100306606A1 COMPACTOR INDEPENDENT DIRECT DIAGNOSIS OF TEST HARDWARE 有权
标题翻译：测试硬件的独立直接诊断测试
公开(公告)号：US20100306606A1
公开(公告)日：2010-12-02
申请号：US12790049
申请日：2010-05-28
申请人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
发明人： Yu Huang , Wu-Tung Cheng , Janusz Rajski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547 , G06F11/267 , G06F11/27
摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于执行故障诊断的方法，装置和系统。在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。可以报告一个或多个识别的扫描单元候选。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

13. 发明申请

US20070234157A1 Multi-stage test response compactors 有权
标题翻译：多级测试响应压实机
公开(公告)号：US20070234157A1
公开(公告)日：2007-10-04
申请号：US11709071
申请日：2007-02-20
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供约1000x的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

14. 发明授权

US07818644B2 Multi-stage test response compactors 有权
标题翻译：多级测试响应压实机
公开(公告)号：US07818644B2
公开(公告)日：2010-10-19
申请号：US11709071
申请日：2007-02-20
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Mark Kassab , Wu-Tung Cheng
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31723 , G01R31/31727 , G01R31/318547 , G01R31/318563 , G01R31/318566
摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.
摘要翻译：这里公开了所谓的“X-press”测试响应压实机的示例性实施例。所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。所公开技术的某些实施例提供大约1000×的压实比。所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

15. 发明授权

US08356222B2 Fault diagnosis for non-volatile memories 有权
标题翻译：非易失性存储器的故障诊断
公开(公告)号：US08356222B2
公开(公告)日：2013-01-15
申请号：US12718822
申请日：2010-03-05
申请人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
发明人： Nilanjan Mukherjee , Artur Pogiel , Janusz Rajski , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G11C29/40 , G11C16/04 , G11C17/14 , G11C29/20 , G11C29/56 , G11C29/56008 , G11C2029/0401 , G11C2029/1208 , G11C2029/5606
摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).
摘要翻译：公开了用于非易失性存储器的故障诊断技术。这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。通过确定性分区，生成签名以识别失败的行，列和单个存储单元。行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

16. 发明申请

US20120272110A1 Test Generator For Low Power Built-In Self-Test 有权
标题翻译：用于低功耗内置自检的测试发生器
公开(公告)号：US20120272110A1
公开(公告)日：2012-10-25
申请号：US13451527
申请日：2012-04-19
申请人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
发明人： Janusz Rajski , Jerzy Tyszer , Grzegorz Mrugalski , Benoit Nadeau-Dostie
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318575 , G01R31/31721 , G01R31/318385 , G01R31/3187
摘要： Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
摘要翻译：本发明的方面涉及基于BIST的低功率测试。低功率测试发生器可以包括伪随机模式发生器单元，触发控制单元，被配置为基于由伪随机模式发生器单元生成的比特序列数据产生切换控制数据;以及保持寄存器单元，被配置为产生低功率测试图案数据通过基于从触发控制单元接收到的切换控制数据，在各种时间段期间以常数值替换来自伪随机模式发生器单元的一些或全部输出的数据。低功率测试发生器还可以包括移相器，其被配置为组合用于驱动扫描链的低功率测试图案数据的位。

17. 发明授权

US08290738B2 Low power scan testing techniques and apparatus 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US08290738B2
公开(公告)日：2012-10-16
申请号：US13049844
申请日：2011-03-16
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F19/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（EDT）架构）集成）。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

18. 发明授权

US08051352B2 Timing-aware test generation and fault simulation 有权
标题翻译：定时识别测试生成和故障模拟
公开(公告)号：US08051352B2
公开(公告)日：2011-11-01
申请号：US11796374
申请日：2007-04-27
申请人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
发明人： Xijiang Lin , Kun-Han Tsai , Mark Kassab , Chen Wang , Janusz Rajski
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328 , G01R31/3177 , G01R31/31835 , G01R31/318357 , G06F17/5009
摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
摘要翻译：这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

19. 发明授权

US07900104B2 Test pattern compression for an integrated circuit test environment 有权
标题翻译：用于集成电路测试环境的测试模式压缩
公开(公告)号：US07900104B2
公开(公告)日：2011-03-01
申请号：US12405409
申请日：2009-03-17
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案。

20. 发明授权

US07877656B2 Continuous application and decompression of test patterns to a circuit-under-test 有权
标题翻译：将测试模式连续应用和解压缩到被测电路
公开(公告)号：US07877656B2
公开(公告)日：2011-01-25
申请号：US12352994
申请日：2009-01-13
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318547
摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.
摘要翻译：在测试电路中将测试图案应用于扫描链的方法。该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并适于接收解压缩的测试图案。

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