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11. 发明授权

US07005704B2 Insulated gate drive semiconductor device 失效
标题翻译：绝缘栅驱动半导体器件
公开(公告)号：US07005704B2
公开(公告)日：2006-02-28
申请号：US10860130
申请日：2004-06-04
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/165 , H01L29/267 , H01L29/739 , H01L29/7393 , H01L29/7804 , H01L29/7806 , H01L29/7808 , H01L29/7813 , H01L29/7827
摘要： An aspect of the present invention provides a semiconductor device includes that a drain region of a first conductivity type formed in a semiconductor substrate, a source region of the first conductivity type, an insulating film in contact with the source region, a gate electrode insulated from the source region by the insulating film, and a base region of a second conductivity type electrically connected to the gate electrode and in contact with the drain region, wherein majority carriers flow between the source region and the drain region before minority carriers are introduced from the base region into the drain region when a predetermined potential is applied to the gate electrode.
摘要翻译：本发明的一个方面提供了一种半导体器件，包括形成在半导体衬底中的第一导电类型的漏极区域，第一导电类型的源极区域，与源极区域接触的绝缘膜，通过绝缘膜的源极区域和与栅极电极连接并与漏极区域接触的第二导电类型的基极区域，其中多数载流子在源极区域和漏极区域之间流过少数载流子从当预定的电位被施加到栅电极时，将漏极区域引入漏区。

12. 发明申请

US20050062048A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050062048A1
公开(公告)日：2005-03-24
申请号：US10947264
申请日：2004-09-23
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L21/04 , H01L29/24 , H01L29/267 , H01L29/78 , H01L21/338 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

13. 发明授权

US07173307B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07173307B2
公开(公告)日：2007-02-06
申请号：US10947264
申请日：2004-09-23
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

14. 发明授权

US07151280B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07151280B2
公开(公告)日：2006-12-19
申请号：US11012205
申请日：2004-12-16
申请人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
发明人： Tetsuya Hayashi , Masakatsu Hoshi , Saichirou Kaneko , Hideaki Tanaka
IPC分类号： H01L31/0312 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7806 , H01L29/1608 , H01L29/165 , H01L29/47 , H01L29/66068 , H01L29/7802 , H01L29/7803 , H01L29/7813 , H01L29/7817 , H01L29/782 , H01L29/7828
摘要： A semiconductor device includes a heterojunction semiconductor region 9, which forms a heterojunction with a drain region 2. The heterojunction semiconductor region 9 is connected to a source electrode 7, and has a band gap different from a band gap of a semiconductor substrate constituting the drain region 2. It is possible to set the size of an energy barrier against conduction electrons, which is formed between the drain region 2 and the heterojunction semiconductor region 9, into a desired size by changing the conductivity type or the impurity density of the heterojunction semiconductor region 9. This is a characteristic not found in a Schottky junction, in which the size of the energy barrier is inherently determined by a work function of a metal material. It is easy to achieve optimal design of a passive element in response to a withstand voltage system of a MOSFET as a switching element. It is also possible to suppress diffusion potential in a reverse conduction mode and to improve a degree of integration per unit area. As a result, it is possible to reduce the size of elements and to simplify manufacturing processes thereof.
摘要翻译：半导体器件包括异质结半导体区域9，其与漏极区域2形成异质结。异质结半导体区域9连接到源电极7，并且具有与构成漏极的半导体衬底的带隙不同的带隙可以通过改变异质结半导体的导电类型或杂质浓度来将能量势垒的大小与形成在漏极区域2和异质结半导体区域9之间的传导电子设置成所需的尺寸这是肖特基结中没有发现的特征，其中能量势垒的尺寸固有地由金属材料的功函数决定。响应MOSFET的耐压系统作为开关元件，很容易实现无源元件的最佳设计。也可以抑制反向导通模式的扩散电位，提高单位面积的积分度。结果，可以减小元件的尺寸并简化其制造工艺。

15. 发明申请

US20060208261A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060208261A1
公开(公告)日：2006-09-21
申请号：US11438347
申请日：2006-05-23
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).
摘要翻译：具有高电流增益hFE的高电压半导体器件由第一导电类型的集电极区域（20），第一导电类型的发射极区域（40）和第二导电类型的基极区域（30）形成与位于集电极区域和发射极区域之间的第一导电类型相反。没有形成耗尽层的基极区域（30）的自由载流子密度小于形成在基极区域（30）中的耗尽层的空间电荷密度。

16. 发明授权

US08507345B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08507345B2
公开(公告)日：2013-08-13
申请号：US13246454
申请日：2011-09-27
申请人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya Hayashi , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L21/336
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

17. 发明申请

US20120021579A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120021579A1
公开(公告)日：2012-01-26
申请号：US13246454
申请日：2011-09-27
申请人： Tetsuya HAYASHI , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
发明人： Tetsuya HAYASHI , Hideaki Tanaka , Masakatsu Hoshi , Saichirou Kaneko
IPC分类号： H01L21/336
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： An aspect of the present invention provides a semiconductor device that includes a first conductivity type semiconductor body, a source region in contact with the semiconductor body, whose bandgap is different from that of the semiconductor body, and which formed heterojunction with the semiconductor body, a gate insulating film in contact with a portion of junction between the source region and the semiconductor body, a gate electrode in contact with the gate insulating film, a source electrode, a low resistance region in contact with the source electrode and the source region, and connected ohmically with the source electrode, and a drain electrode connected ohmically with the semiconductor body.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括第一导电型半导体本体，与半导体本体接触的源极区域，其带隙与半导体本体的带隙不同，并且与半导体本体形成异质结，与栅极绝缘膜接触的栅电极，源电极，与源极电极和源极区域接触的低电阻区域，以及与源电极欧姆连接，以及与半导体主体欧姆连接的漏电极。

18. 发明授权

US07071536B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US07071536B2
公开(公告)日：2006-07-04
申请号：US10772283
申请日：2004-02-06
申请人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
发明人： Saichirou Kaneko , Masakatsu Hoshi , Yoshinori Murakami , Tetsuya Hayashi , Hideaki Tanaka
IPC分类号： H01L27/082
CPC分类号： H01L29/1608 , H01L29/1004 , H01L29/6606 , H01L29/66068 , H01L29/66234 , H01L29/7322 , H01L29/861
摘要： A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposite to the first conduction type located between the collector region and the emitter region. The free carrier density of the base region (30) where no depletion layer is formed is smaller than the space charge density of a depletion layer formed in the base region (30).

19. 发明申请

US20100001315A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100001315A1
公开(公告)日：2010-01-07
申请号：US12473604
申请日：2009-05-28
申请人： Masaaki OKITA , Kazuyuki Sawada , Yuji Harada , Saichirou Kaneko , Hiroto Yamagiwa
发明人： Masaaki OKITA , Kazuyuki Sawada , Yuji Harada , Saichirou Kaneko , Hiroto Yamagiwa
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/0692 , H01L29/7393 , H01L29/7835 , H01L2029/42388 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first diffusion region of a second conductivity type formed in an upper portion of a semiconductor substrate of a first conductivity type, a second diffusion region formed in a surface portion of the first diffusion region, a third diffusion region of the second conductivity type formed a predetermined distance spaced apart from the second diffusion region in the surface portion of the semiconductor substrate, a fourth diffusion region of the first conductivity type formed adjacent to the third diffusion region and electrically connected to the third diffusion region, a gate electrode formed on a part between the first diffusion region and the third diffusion region, and an insulating film formed thereon. The impurity concentration of the first diffusion region is set higher than an impurity concentration at which a depletion region extending from an junction interface between the first diffusion region and the semiconductor substrate is formed in a part of the first diffusion region which is between the second diffusion region and the gate electrode when a voltage is applied to the second diffusion region.
摘要翻译：半导体器件包括形成在第一导电类型的半导体衬底的上部中的第二导电类型的第一扩散区域，形成在第一扩散区域的表面部分中的第二扩散区域，第二扩散区域的第二扩散区域在半导体衬底的表面部分形成与第二扩散区间隔开的预定距离的导电类型，与第三扩散区相邻形成并与第三扩散区电连接的第一导电类型的第四扩散区，栅电极形成在第一扩散区域和第三扩散区域之间的部分上，以及形成在其上的绝缘膜。将第一扩散区域的杂质浓度设定为高于从第一扩散区域和半导体衬底之间的结界面延伸的耗尽区域形成在第一扩散区域的位于第二扩散区域的部分之间的杂质浓度区域和栅电极，当电压施加到第二扩散区域时。

20. 发明授权

US07485895B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US07485895B2
公开(公告)日：2009-02-03
申请号：US11822922
申请日：2007-07-11
申请人： Saichirou Kaneko
发明人： Saichirou Kaneko
IPC分类号： H01L29/15
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A silicon carbide semiconductor device is provided with a semiconductor substrate (20) of silicon carbide of a first conductivity type, a hetero semiconductor region (60) forming a hetero-junction with the semiconductor substrate (20), an insulated gate including a gate electrode (40) and a gate insulator layer (30) formed on the semiconductor substrate (20) and adjoining to the hetero semiconductor region (60), a source electrode (80) electrically connected to the hetero semiconductor region (60) and a drain electrode (90) electrically connected to the semiconductor substrate (20).
摘要翻译：碳化硅半导体器件设置有第一导电类型的碳化硅的半导体衬底（20），与半导体衬底（20）形成异质结的异质半导体区（60），包括栅电极（40）和形成在所述半导体衬底（20）上并与所述异质半导体区域（60）相邻的栅极绝缘体层（30），与所述异质半导体区域（60）电连接的源电极（80）（90），电连接到半导体衬底（20）。

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