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11. 发明授权

US6093652A Methods of forming insulative plugs, and oxide plug forming methods 有权
标题翻译：形成绝缘塞的方法和氧化物塞形成方法
公开(公告)号：US6093652A
公开(公告)日：2000-07-25
申请号：US146765
申请日：1998-09-03
申请人： Pai-Hung Pan , Whonchee Lee
发明人： Pai-Hung Pan , Whonchee Lee
IPC分类号： H01L21/306 , H01L21/3105 , H01L21/316 , H01L21/762 , H01L21/00
CPC分类号： H01L21/76224 , H01L21/30604 , H01L21/31053 , H01L21/31612
摘要： In one aspect, the invention includes a method of forming an insulative plug within a substrate, comprising: a) forming a masking layer over the substrate, the masking layer having an opening extending therethrough to expose a portion of the underlying substrate; b) etching the exposed portion of the underlying substrate to form an opening extending into the substrate; c) forming an insulative material within the opening in the substrate, the insulative material within the opening forming an insulative plug within the substrate; d) after forming the insulative material within the opening, removing the masking layer; and e) after removing the masking layer, removing a portion of the substrate to lower an upper surface of the substrate relative to the insulative plug.
摘要翻译：在一个方面，本发明包括一种在衬底内形成绝缘插塞的方法，包括：a）在衬底上形成掩模层，掩模层具有穿过其中的开口以露出下面衬底的一部分; b）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; c）在所述基板的开口内形成绝缘材料，所述开口内的所述绝缘材料在所述基板内形成绝缘塞; d）在开口内形成绝缘材料之后，去除掩模层; 以及e）在去除掩蔽层之后，去除衬底的一部分以相对于绝缘插头降低衬底的上表面。

12. 发明授权

US5998844A Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon 有权
标题翻译：包括具有单晶和多晶硅的导电插塞的半导体结构
公开(公告)号：US5998844A
公开(公告)日：1999-12-07
申请号：US153088
申请日：1998-09-14
申请人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
发明人： Kirk Prall , Pai-Hung Pan , Sujit Sharan
IPC分类号： H01L21/225 , H01L21/336 , H01L29/08 , H01L29/43
CPC分类号： H01L29/66628 , H01L21/2257 , H01L29/0847 , Y10S438/969
摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated fin electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.
摘要翻译：一种形成场效应晶体管相对于单晶硅衬底的方法，其中晶体管具有升高的源极和升高的漏极，其包括：a）在单晶硅衬底上提供晶体管栅极，栅极是封装的鳍状电绝缘材料; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内，并且在清洁步骤之后，化学气相沉积导电掺杂的非多晶硅层在与晶体管栅极相邻的清洁的衬底表面上，非多晶硅层具有外表面，衬底不在清洁时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。还要求一种场效应晶体管。

13. 发明授权

US5834358A Isolation regions and methods of forming isolation regions 失效
公开(公告)号：US5834358A
公开(公告)日：1998-11-10
申请号：US745716
申请日：1996-11-12
申请人： Pai-Hung Pan , Karl M. Robinson
发明人： Pai-Hung Pan , Karl M. Robinson
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an upper surface of a substrate immediately adjacent the trenched isolation region. An oxide plug is formed comprising a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface. The elevated portion comprising a ledge which extends over the substrate upper surface and has a top surface and a substantially vertical lateral edge side surface. Further, the plug may be within a substrate, the oxide plug having a recessed portion below a substrate upper surface and an elevated portion above the substrate upper surface, the elevated portion comprising a ledge extending over the substrate upper surface and abutting a polysilicon layer.

14. 发明授权

US5741738A Method of making corner protected shallow trench field effect transistor 失效
标题翻译：制造角保护浅沟槽场效应晶体管的方法
公开(公告)号：US5741738A
公开(公告)日：1998-04-21
申请号：US604283
申请日：1996-02-21
申请人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael M. Armacost , Pai-Hung Pan
发明人： Jack A. Mandelman , Brian J. Machesney , Hing Wong , Michael M. Armacost , Pai-Hung Pan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.
摘要翻译：一种用于防止栅包绕和角寄生泄漏的半导体结构，包括具有平坦表面的半导体衬底。沟槽位于衬底中，沟槽具有侧壁。沟槽和表面的交点形成一个角落。介电线路沟槽的侧壁。并且，与拐角共同对准的拐角电介质在拐角处延伸超过衬底的最小尺寸距离。

15. 发明授权

US5686345A Trench mask for forming deep trenches in a semiconductor substrate, and method of using same 失效
标题翻译：用于在半导体衬底中形成深沟槽的沟槽掩模及其使用方法
公开(公告)号：US5686345A
公开(公告)日：1997-11-11
申请号：US593944
申请日：1996-01-30
申请人： David Laurant Harmon , Nancy Tovey Pascoe , John Francis Rembetski , Pai-Hung Pan
发明人： David Laurant Harmon , Nancy Tovey Pascoe , John Francis Rembetski , Pai-Hung Pan
IPC分类号： H01L21/308 , H01L21/76
CPC分类号： H01L21/3081 , Y10S148/05
摘要： A method for forming high aspect ratio, deep trenches in a semiconductor substrate with a composite etch mask structure including a thermally grown oxide surface layer as a plasma etch mask.
摘要翻译：一种用于通过复合蚀刻掩模结构在半导体衬底中形成高纵横比的方法，该掩模结构包括热生长的氧化物表面层作为等离子体蚀刻掩模。

16. 发明授权

US5434109A Oxidation of silicon nitride in semiconductor devices 失效
标题翻译：半导体器件中氮化硅的氧化
公开(公告)号：US5434109A
公开(公告)日：1995-07-18
申请号：US54112
申请日：1993-04-27
申请人： Stephen F. Geissler , Josef W. Korejwa , Jerome B. Lasky , Pai-Hung Pan
发明人： Stephen F. Geissler , Josef W. Korejwa , Jerome B. Lasky , Pai-Hung Pan
IPC分类号： H01L21/318 , H01L21/314 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/02
CPC分类号： H01L21/3144
摘要： A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600.degree. C. is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF.sub.3 is the fluorine-containing compound, and a temperature greater than about 700.degree. C. at a concentration of between about 100 to 1000 ppm is used.
摘要翻译：半导体器件中的氮化硅层通过在足够高的温度下暴露于氧反应物和稀释的含氟化合物的混合物而被氧化，从而基本上导致氮化硅的氧化。通常，大于约600℃的温度足以引起这种氧化，尽管在较低温度下可能发生一些氧化。含氟化合物的浓度也不是关键的，但相对于总混合物体积通常为约100至1500ppm体积。优选地，NF 3是含氟化合物，并且使用浓度在约100至1000ppm之间的大于约700℃的温度。

17. 发明授权

US4631219A Growth of bird's beak free semi-rox 失效
标题翻译：鸟喙自由半生长的增长
公开(公告)号：US4631219A
公开(公告)日：1986-12-23
申请号：US696824
申请日：1985-01-31
申请人： Henry J. Geipel, Jr. , Pai-Hung Pan
发明人： Henry J. Geipel, Jr. , Pai-Hung Pan
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L21/32 , H01L21/762 , B32B15/04
CPC分类号： H01L21/76202 , H01L21/3144 , H01L21/32 , Y10T428/24273 , Y10T428/24322 , Y10T428/24777
摘要： An oxygen-impervious pad structure which reduces the bird's beak profiles in semi-recessed oxide isolation regions. The sidewalls of a conventional silicon oxide - silicon nitride pad are coated with a thick layer of oxynitride. A thin layer of oxynitride is grown on the substrate surface prior to deposition of the thick oxynitride layer. The thick oxynitride layer prevents lateral oxidizing specie diffusion through the oxide layer of the conventional pad, and the thin oxynitride layer prevents lateral oxidizing specie diffusion through the pad-substrate interface into the substrate region beneath the pad.
摘要翻译：一种不透氧的垫结构，可减少半凹陷氧化物隔离区域中的鸟嘴形貌。常规氧化硅 - 氮化硅垫的侧壁涂覆有厚氮氧化物层。在沉积厚氮氧化物层之前，在衬底表面上生长薄氮氧化物。厚氧氮化物层防止横向氧化物质扩散通过常规焊盘的氧化物层，并且薄氧氮化物层防止横向氧化物质通过焊盘 - 衬底界面扩散到焊盘下方的衬底区域中。

18. 发明授权

US07132035B2 Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using mechanical and chemical-mechanical planarization processes 有权
公开(公告)号：US07132035B2
公开(公告)日：2006-11-07
申请号：US09789359
申请日：2001-02-20
申请人： Karl M. Robinson , Pai-Hung Pan
发明人： Karl M. Robinson , Pai-Hung Pan
IPC分类号： C23F1/00 , B24B49/00
CPC分类号： B24B37/013 , B24B49/16 , H01L21/2007 , H01L21/31053 , H01L21/76224
摘要： Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped. The first change in drag force between the substrate assembly and the planarizing medium is preferably detected by measuring a first change in the electrical current through a drive motor driving a substrate holder carrying the substrate assembly and/or a table carrying the polishing pad. The second change in drag force between the substrate assembly and the polishing pad may be identified by detecting a second change in the drive motor current or measuring a second change in the temperature of the planarizing solution or the polishing pad.

19. 发明授权

US06764934B2 Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random 失效
标题翻译：形成接触开口的半导体加工方法，形成存储器电路的方法，形成电连接的方法以及形成动态随机存取存储器（电容）电路的方法
公开(公告)号：US06764934B2
公开(公告)日：2004-07-20
申请号：US10137100
申请日：2002-05-01
申请人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
发明人： Pai-Hung Pan , Luan C. Tran , Tyler A. Lowrey
IPC分类号： H04L2144
CPC分类号： H01L27/10888 , H01L21/32051 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.
摘要翻译：描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

20. 发明授权

US06436831B1 Methods of forming insulative plugs and oxide plug forming methods 失效
标题翻译：形成绝缘塞的方法和氧化物塞形成方法
公开(公告)号：US06436831B1
公开(公告)日：2002-08-20
申请号：US09528740
申请日：2000-03-20
申请人： Pai-Hung Pan , Whonchee Lee
发明人： Pai-Hung Pan , Whonchee Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/30604 , H01L21/31053 , H01L21/31612
摘要： In one aspect, the invention includes a method of forming an insulative plug within a substrate, comprising: a) forming a masking layer over the substrate, the masking layer having an opening extending therethrough to expose a portion of the underlying substrate; b) etching the exposed portion of the underlying substrate to form an opening extending into the substrate; c) forming an insulative material within the opening in the substrate, the insulative material within the opening forming an insulative plug within the substrate; d) after forming the insulative material within the opening, removing the masking layer; and e) after removing the masking layer, removing a portion of the substrate to lower an upper surface of the substrate relative to the insulative plug.
摘要翻译：在一个方面，本发明包括一种在衬底内形成绝缘插塞的方法，包括：a）在衬底上形成掩模层，掩模层具有穿过其中的开口以露出下面衬底的一部分; b）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; c）在所述基板的开口内形成绝缘材料，所述开口内的所述绝缘材料在所述基板内形成绝缘塞; d）在开口内形成绝缘材料之后，去除掩模层; 以及e）在去除掩蔽层之后，去除衬底的一部分以相对于绝缘插头降低衬底的上表面。

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