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11. 发明申请

US20050280082A1 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US20050280082A1
公开(公告)日：2005-12-22
申请号：US11167640
申请日：2005-06-27
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L21/265 , H01L21/336 , H01L29/04 , H01L29/76 , H01L29/772
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

12. 发明授权

US09269770B2 Integrated circuit system with double doped drain transistor 有权
标题翻译：具有双掺杂漏极晶体管的集成电路系统
公开(公告)号：US09269770B2
公开(公告)日：2016-02-23
申请号：US11683655
申请日：2007-03-08
申请人： Yisuo Li , Gang Chen , Francis Benistant , Purakh Raj Verma , Hong Yang , Shao-fu Sanford Chu
发明人： Yisuo Li , Gang Chen , Francis Benistant , Purakh Raj Verma , Hong Yang , Shao-fu Sanford Chu
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78 , H01L29/739
CPC分类号： H01L29/0847 , H01L29/0843 , H01L29/6659 , H01L29/66681 , H01L29/7393 , H01L29/7816 , H01L29/7833
摘要： An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.
摘要翻译：集成电路系统包括：衬底，在衬底上形成栅极，形成具有第一反扩散区域和源极扩散区域的第一漂移区域，邻近栅极第一侧的衬底中的第一漂移区域，以及形成第二漂移区域，具有第二反扩散区域和漏扩散区域，所述衬底中的所述第二漂移区域邻近所述栅极的与所述栅极的第一侧相对的第二侧。

13. 发明授权

US07573099B2 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US07573099B2
公开(公告)日：2009-08-11
申请号：US11170576
申请日：2005-06-28
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L29/48 , H01L27/088
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

14. 发明授权

US07259072B2 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability 有权
标题翻译：浅层低能离子注入衬垫氧化物，以提高阈值电压稳定性
公开(公告)号：US07259072B2
公开(公告)日：2007-08-21
申请号：US10828887
申请日：2004-04-21
申请人： Yisuo Li , Francis Benistant , Kim Hyun Sik , Zhao Lun
发明人： Yisuo Li , Francis Benistant , Kim Hyun Sik , Zhao Lun
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/823807 , H01L21/823892 , H01L29/78
摘要： A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.
摘要翻译：描述了一种制造具有增加的阈值电压稳定性的MOSFET器件的方法。在衬底氧化物和衬垫氮化物沉积在硅衬底上并且浅沟槽被图案化并且去除衬垫氮化物之后。然后使用约5keV的低能离子注入到垫氧化物中，将 + /或P + + / 常规作为 +或/或P / N>植入物沿着浅植入物形成n孔。通过形成牺牲浅注入氧化物层的方法，使衬底氧化物：硅衬底界面处的表面掺杂剂浓度变化最小化; 并且器件的阈值电压稳定性变化显着降低。

15. 发明授权

US07253483B2 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US07253483B2
公开(公告)日：2007-08-07
申请号：US11167640
申请日：2005-06-27
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

16. 发明申请

US20050239256A1 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability 有权
标题翻译：浅层低能离子注入衬垫氧化物，以提高阈值电压稳定性
公开(公告)号：US20050239256A1
公开(公告)日：2005-10-27
申请号：US10828887
申请日：2004-04-21
申请人： Yisuo Li , Francis Benistant , Kim Sik , Zhao Lun
发明人： Yisuo Li , Francis Benistant , Kim Sik , Zhao Lun
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/2652 , H01L21/823807 , H01L21/823892 , H01L29/78
摘要： A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.
摘要翻译：描述了一种制造具有增加的阈值电压稳定性的MOSFET器件的方法。在衬底氧化物和衬垫氮化物沉积在硅衬底上并且浅沟槽被图案化并且去除衬垫氮化物之后。然后使用约5keV的低能离子注入到垫氧化物中，将 + /或P + + / 常规作为 +或/或P / N>植入物沿着浅植入物形成n孔。通过形成牺牲浅注入氧化物层的方法，使衬底氧化物：硅衬底界面处的表面掺杂剂浓度变化最小化; 并且器件的阈值电压稳定性变化显着降低。

17. 发明授权

US08994107B2 Semiconductor devices and methods of forming the semiconductor devices including a retrograde well 有权
标题翻译：形成包括逆行井的半导体器件的半导体器件和方法
公开(公告)号：US08994107B2
公开(公告)日：2015-03-31
申请号：US13595208
申请日：2012-08-27
申请人： El Mehdi Bazizi , Francis Benistant
发明人： El Mehdi Bazizi , Francis Benistant
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66
CPC分类号： H01L29/6659 , H01L29/105 , H01L29/1054 , H01L29/7836
摘要： Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
摘要翻译：本文提供半导体器件和半导体器件形成方法。在一个实施例中，半导体器件包括半导体衬底。源极区域和漏极区域设置在半导体衬底中。在源极区域和漏极区域之间的半导体衬底中限定沟道区域。栅极电介质层覆盖在半导体衬底的沟道区域上，栅电极覆盖在栅介电层上。沟道区包括第一含碳层，覆盖第一含碳层的掺杂层，覆盖掺杂层的第二含碳层和覆盖第二含碳层的本征半导体层。掺杂层包括不同于碳的掺杂剂。

18. 发明授权

US08053340B2 Method for fabricating semiconductor devices with reduced junction diffusion 有权
标题翻译：制造具有减小的结扩散的半导体器件的方法
公开(公告)号：US08053340B2
公开(公告)日：2011-11-08
申请号：US11862213
申请日：2007-09-27
申请人： Benjamin Colombeau , Sai Hooi Yeong , Francis Benistant , Bangun Indajang , Lap Chan
发明人： Benjamin Colombeau , Sai Hooi Yeong , Francis Benistant , Bangun Indajang , Lap Chan
IPC分类号： H01L21/425 , H01L21/22 , H01L21/38
CPC分类号： H01L29/78612 , H01L29/66537 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.
摘要翻译：一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。晕区具有上部和下部区域。上部区域是具有多余空位的结晶区域，下部区域是非晶区域。源极/漏极扩散区域设置在光晕区域中。源极/漏极扩散区域与上部和下部晕圈重叠。该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

19. 发明授权

US07037860B2 Modified source/drain re-oxidation method and system 失效
公开(公告)号：US07037860B2
公开(公告)日：2006-05-02
申请号：US10818564
申请日：2004-04-06
申请人： Paul J. Rudeck , Francis Benistant , Kelly Hurley
发明人： Paul J. Rudeck , Francis Benistant , Kelly Hurley
IPC分类号： H01L21/31 , H01L21/469 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/02129 , H01L21/022 , H01L21/0234 , H01L21/31625 , H01L27/115 , H01L27/11521 , H01L29/6659 , H01L29/66659 , H01L29/66825
摘要： Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation process and greater control of the performance characteristics of semiconductor devices such as flash memory. For flash memory, greater control is gained over programming rates, erase rates, data retention and self align source resistance.

20. 发明授权

US06969646B2 Method of activating polysilicon gate structure dopants after offset spacer deposition 失效
标题翻译：在偏移间隔物沉积后激活多晶硅栅极结构掺杂剂的方法
公开(公告)号：US06969646B2
公开(公告)日：2005-11-29
申请号：US10361877
申请日：2003-02-10
申请人： Elgin Quek , Francis Benistant
发明人： Elgin Quek , Francis Benistant
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L31/0328
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A process sequence used to integrate an anneal cycle, used to activate ion implanted dopants in a polysilicon gate structure, and the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure, has been developed. The process sequence features ion implantation of dopants into a blanket polysilicon layer located overlying a metal oxide semiconductor field effect transistor (MOSFET), gate insulator layer. After definition of the polysilicon gate structure a silicon oxide layer is deposited, followed by an anneal procedure allowing activation of the implanted dopants in the polysilicon gate structure to occur. Out diffusion of implanted dopants during the activation anneal procedure is minimized as a result of the overlying silicon oxide layer. An anisotropic dry etching procedure is then performed on the silicon oxide layer resulting in the definition of offset silicon oxide spacers on the sides of the polysilicon gate structure.
摘要翻译：已经开发了用于整合用于激活多晶硅栅极结构中的离子注入掺杂剂的退火循环的处理顺序以及多晶硅栅极结构侧面上的偏移氧化硅间隔物的定义。工艺顺序的特征是将掺杂剂离子注入位于覆盖金属氧化物半导体场效应晶体管（MOSFET）栅极绝缘体层的覆盖多晶硅层中。在多晶硅栅极结构的定义之后，沉积氧化硅层，随后进行退火程序，允许在多晶硅栅极结构中激发注入的掺杂剂。在激活退火过程中注入的掺杂剂的扩散由于上覆的氧化硅层而被最小化。然后在氧化硅层上进行各向异性的干法蚀刻，得到多晶硅栅极结构侧面的偏移氧化硅间隔物的定义。

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