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11. 发明授权

US5798192A Structure of a mask for use in a lithography process of a semiconductor fabrication 失效
标题翻译：用于半导体制造的光刻工艺中的掩模的结构
公开(公告)号：US5798192A
公开(公告)日：1998-08-25
申请号：US834330
申请日：1997-04-15
申请人： Ming-Chu King , Shih-Shiung Chen , Ying-Chen Chao
发明人： Ming-Chu King , Shih-Shiung Chen , Ying-Chen Chao
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/40 , G03F1/50
摘要： A structure of a mask for use in a lithography process in a semiconductor fabrication procedure is disclosed. The structure comprising: a mask base being made of transparent material; a plurality of patterns formed on said mask base, said patterns being used for generating an image on a wafer and being made of a conductive opaque material; and a conductive layer formed on said mask base and said plurality of patterns.
摘要翻译：公开了一种用于半导体制造过程中的光刻工艺中的掩模的结构。该结构包括：掩模基底，由透明材料制成; 形成在所述掩模基底上的多个图案，所述图案用于在晶片上产生图像并由导电不透明材料制成; 以及形成在所述掩模基底和所述多个图案上的导电层。

12. 发明授权

US06604853B2 Accelerated thermal stress cycle test 有权
公开(公告)号：US06604853B2
公开(公告)日：2003-08-12
申请号：US09976995
申请日：2001-10-11
申请人： Ying-Chen Chao , Wi William Lee , Sen-Shan Yang , Keng-Hui Liao
发明人： Ying-Chen Chao , Wi William Lee , Sen-Shan Yang , Keng-Hui Liao
IPC分类号： G01N1700
CPC分类号： G01N3/60 , G01N2033/0095
摘要： An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350° C. in an inert gas in about 2 min., and then cooled down to not higher than 70° C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

13. 发明授权

US5999397A Method for preventing electrostatic discharge damage to an insulating article 失效
标题翻译：防止静电放电损坏绝缘物品的方法
公开(公告)号：US5999397A
公开(公告)日：1999-12-07
申请号：US958531
申请日：1997-10-27
申请人： Ming-Fa Chen , Shih-Shiung Chen , Ying-Chen Chao
发明人： Ming-Fa Chen , Shih-Shiung Chen , Ying-Chen Chao
IPC分类号： G03F7/20 , H05F1/00
CPC分类号： G03F1/66 , G03F7/70741 , H05F1/00
摘要： The present invention discloses a method for preventing electrostatic discharge damages to an article that is made of an insulating material and stored in a container also made of an insulating material by maintaining a minimum safe distance between the article and the top lid of the container such that a saturation electric field cannot be reached at such safety distance and thus electrostatic discharge does not occur. The present invention novel method can be utilized in carrying any insulating articles but is particularly suitable for carrying a quartz reticle in a polycarbonate pod.
摘要翻译：本发明公开了一种防止对由绝缘材料制成的物品的静电放电损坏的方法，并且通过保持物品与容器顶盖之间的最小安全距离而将其储存在也由绝缘材料制成的容器中，使得在这样的安全距离处不能达到饱和电场，因此不会发生静电放电。本发明的新颖方法可用于承载任何绝缘制品，但特别适用于在聚碳酸酯荚中承载石英掩模版。

14. 发明授权

US5693976A MOSFET device having denuded zones for forming alignment marks 失效
标题翻译： MOSFET器件具有用于形成对准标记的剥离区域
公开(公告)号：US5693976A
公开(公告)日：1997-12-02
申请号：US720265
申请日：1996-09-26
申请人： Ying-Chen Chao
发明人： Ying-Chen Chao
IPC分类号： H01L21/8238 , H01L21/84 , H01L29/80 , H01L23/58 , H01L29/76
CPC分类号： H01L21/84 , H01L21/823871 , H01L21/823878 , H01L2924/0002 , Y10S148/024
摘要： A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded zone, low temperature processing had to be used. Low temperature insulator depositions were used for the alignment mark formation, as well as for the fill for the field oxide regions. Subsequently, high temperature well formation activation anneals, resulted in the creation of the denuded zone, and thus removed the low temperature restriction for the remaining processing steps.
摘要翻译：已经开发了用于制造其中在正常工艺序列期间已经形成硅中的裸露区域的MOSFET器件的工艺。为了避免有害的氧沉淀物的形成，在形成剥离区之前，必须使用低温处理。低温绝缘体沉积用于对准标记形成，以及用于场氧化物区域的填充。随后，高温井形成激活退火，导致形成剥离区，从而消除了剩余加工步骤的低温限制。

15. 发明授权

US08785235B2 Apparatus and method for producing solar cells 有权
标题翻译：用于生产太阳能电池的装置和方法
公开(公告)号：US08785235B2
公开(公告)日：2014-07-22
申请号：US13486079
申请日：2012-06-01
申请人： Edward Teng , Ying-Chen Chao , Chih-Jen Yang , Kuo-Jui Hsiao
发明人： Edward Teng , Ying-Chen Chao , Chih-Jen Yang , Kuo-Jui Hsiao
IPC分类号： H01L21/00 , H01L31/0264 , H01L21/02 , H01L21/28
CPC分类号： H01L31/18 , C23C14/0623 , C23C14/185 , C23C14/24 , C23C14/3464 , C23C14/505 , H01L21/02104 , H01L21/02631 , H01L21/28194 , H01L21/67011 , H01L21/67155 , H01L31/0322 , H01L31/0326 , Y02E10/541 , Y02P70/521
摘要： A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces wherein each of the plurality of surfaces are disposed facing an interior surface of the vacuum chamber. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is disposed in a first subchamber of the vacuum chamber and configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. A first isolation source is configured to isolate the evaporation source from the first sputtering source.
摘要翻译：一种用于形成太阳能电池的方法和装置。该装置包括限定真空室的壳体和被配置为将多个基板保持在多个表面上的可旋转基板装置，其中多个表面中的每一个面向真空室的内表面设置。第一溅射源被配置成在多个基板中的每个基板的表面的至少一部分上沉积第一类型的多个吸收层原子。蒸发源设置在真空室的第一子室中并且被配置为在多个基板中的每一个的表面的至少一部分上沉积第二类型的多个吸收层原子。第一隔离源被配置为将蒸发源与第一溅射源隔离。

16. 发明授权

US06176141B1 Method for stud pull test for film formed on semiconductor device 有权
标题翻译：半导体器件上形成的薄膜螺柱拉拔试验方法
公开(公告)号：US06176141B1
公开(公告)日：2001-01-23
申请号：US09332379
申请日：1999-06-14
申请人： Lung-Hsiang Chuang , Chung-Long Chang , Syun-Ming Jang , Ying-Chen Chao
发明人： Lung-Hsiang Chuang , Chung-Long Chang , Syun-Ming Jang , Ying-Chen Chao
IPC分类号： G01N300
CPC分类号： G01N3/00 , G01N19/04 , G01N2203/0017 , G01N2203/0091 , G01N2203/0282 , G01N2203/0286 , G01N2203/0296 , G01N2203/0429
摘要： A test sample with a film and an underlying substrate representing part of a semiconductor wafer is prepared for a stud pull test by a process that includes maintaining the sample in boiling salt water for a few hours. When an epoxy stud is attached to the film of the sample and the clamped assembly is baked for a about an hour, the stud is firmly attached to the film and in an otherwise conventional pull test, the film breaks loose from the substrate (or the stud breaks from the epoxy) before the stud breaks from the film.
摘要翻译：制备具有膜和表示半导体晶片的一部分的底层基板的测试样品用于通过包括将样品保持在沸腾的盐水中几个小时的方法进行螺柱拉拔测试。当将环氧树脂柱连接到样品的膜上并且夹持的组件烘烤约1小时时，螺柱牢固地附接到膜上，并且以其它常规的拉伸试验，膜从基板（或在螺柱从胶片上脱落之前，螺柱与环氧树脂断裂。

17. 发明授权

US5807787A Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation 失效
标题翻译：在聚酰亚胺钝化期间减少半导体集成电路上的表面泄漏电流的方法
公开(公告)号：US5807787A
公开(公告)日：1998-09-15
申请号：US755862
申请日：1996-12-02
申请人： Wen-Jui Fu , Ho-Ku Lan , Ying-Chen Chao
发明人： Wen-Jui Fu , Ho-Ku Lan , Ying-Chen Chao
IPC分类号： H01L21/311 , H01C21/4762
CPC分类号： H01L21/31138 , Y10S438/974
摘要： A method is achieved for reducing the surface leakage current between adjacent bonding pads on integrated circuit substrates after forming a patterned polyimide passivation layer. When the polyimide layer is patterned to open contacts areas over the bonding pads, plasma ashing in oxygen is used to remove residual polyimide that otherwise causes high contact resistance, and poor chip yield. This plasma ashing also modifies the insulating layer between bonding pads resulting in an unwanted increase in surface leakage currents between bonding pads. The passivation process is improved by using a thermal treatment step in either a nitrogen or air ambient after the plasma ashing to essentially eliminate the increased surface leakage current and improve chip yield.
摘要翻译：在形成图案化的聚酰亚胺钝化层之后，实现了一种降低集成电路基板上的相邻焊盘之间的表面泄漏电流的方法。当将聚酰亚胺层图案化以在接合焊盘上打开接触区域时，使用氧气中的等离子体灰化来除去残留的聚酰亚胺，否则会导致高接触电阻和较差的芯片产量。该等离子体灰化还修改接合焊盘之间的绝缘层，导致焊盘之间的表面泄漏电流的不期望的增加。通过在等离子体灰化之后在氮气或空气环境中使用热处理步骤来基本上消除增加的表面泄漏电流并提高芯片产量来改善钝化过程。

18. 发明授权

US5790417A Method of automatic dummy layout generation 失效
标题翻译：自动虚拟布局生成方法
公开(公告)号：US5790417A
公开(公告)日：1998-08-04
申请号：US718735
申请日：1996-09-25
申请人： Ying-Chen Chao , Chia-Hsiang Chen , Jhy-Sheng Sheu
发明人： Ying-Chen Chao , Chia-Hsiang Chen , Jhy-Sheng Sheu
IPC分类号： G06F17/50 , H01L23/528
CPC分类号： G06F17/5068 , H01L23/528 , H01L2924/0002
摘要： A method is provided for producing a dummy pattern for an I.C. semiconductor device multi-layer interconnection metallurgy, having a planar global top surface with a dummy pattern for a circuit for use with conductor lines in the circuit pattern. Create a reverse pattern which is a complement of a widened conductor lines in the circuit pattern with openings about the location of the circuit pattern and provide a dummy cross grid pattern. A gridded dummy pattern is generated by creating a dummy grid pattern of the reverse pattern combining it with the negative of the dummy cross grid pattern leaving a cross grid of dummy elements and openings about the location of the circuit pattern. Provide a revised pattern by adding the circuit pattern to the gridded dummy pattern. Take the product of a contact layout pattern multiplied times the sizing operator multiplied times a separation parameter. Then subtract the sized and separated contact layout pattern from the gridded dummy pattern. Then multiply the dummy pattern times a function of sizing operators, and provide a revised contact and circuit pattern by adding the circuit pattern to the sized dummy pattern.
摘要翻译：提供了一种用于产生I.C.的虚拟图案的方法。半导体器件多层互连冶金，具有平面全局顶表面，其具有用于电路图案中的导线的电路的虚拟图案。创建一个反向图案，该反向图案是电路图案中的加宽导体线的补码，其中围绕电路图案的位置具有开口并提供虚拟的交叉格局图案。通过创建反向图案的虚拟网格图案来生成网格虚拟图案，其将虚拟网格图案与虚拟十字网格图案的负片组合，留下围绕电路图案的位置的虚拟元素和开口的十字网格。通过将电路图案添加到网格的虚拟图案中来提供修改的图案。将联系人布局图案乘以倍数乘以乘以分离参数的乘积。然后从网格虚拟模式中减去大小和分隔的联系人布局模式。然后将虚拟图案乘以尺寸操作符的函数，并通过将电路图案添加到大小的虚拟图案中来提供修改的接触和电路图案。

19. 发明授权

US5567643A Method of forming contamination guard ring for semiconductor integrated circuit applications 失效
标题翻译：形成用于半导体集成电路应用的防护环的方法
公开(公告)号：US5567643A
公开(公告)日：1996-10-22
申请号：US251039
申请日：1994-05-31
申请人： Jin-Yuan Lee , John C.-S. Wei , Ying-Chen Chao
发明人： Jin-Yuan Lee , John C.-S. Wei , Ying-Chen Chao
IPC分类号： H01L23/525 , H01L23/544 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5258 , H01L23/5256 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： The guard ring is a barrier which prevents contaminates from diffusing through a window opening through insulating layers to adjacent semiconductor devices. The guard ring is formed surrounding a window in the insulation layers over a fuse link or an alignment mark. The guard ring is an annular metal ring that penetrates two or more insulating layers and contacts the substrate.
摘要翻译：防护环是防止污染物通过绝缘层通过窗口扩散到相邻半导体器件的屏障。保护环形成在保险丝层或对准标记之间的绝缘层中的窗口周围。保护环是穿过两个或更多个绝缘层并与衬底接触的环形金属环。

20. 发明授权

US5478762A Method for producing patterning alignment marks in oxide 失效
标题翻译：用于在氧化物中制造图形对准标记的方法
公开(公告)号：US5478762A
公开(公告)日：1995-12-26
申请号：US405076
申请日：1995-03-16
申请人： Ying-Chen Chao
发明人： Ying-Chen Chao
IPC分类号： H01L21/8238 , H01L21/84
CPC分类号： H01L21/84 , H01L21/823871 , H01L21/823878 , H01L2924/0002 , Y10S148/024
摘要： A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded zone, low temperature processing had to be used. Low temperature insulator depositions were used for the alignment mark formation, as well as for the fill for the field oxide regions. Subsequently, high temperature well formation activation anneals, resulted in the creation of the denuded zone, and thus removed the low temperature restriction for the remaining processing steps.
摘要翻译：已经开发了用于制造其中在正常工艺序列期间已经形成硅中的裸露区域的MOSFET器件的工艺。为了避免有害的氧沉淀物的形成，在形成剥离区之前，必须使用低温处理。低温绝缘体沉积用于对准标记形成，以及用于场氧化物区域的填充。随后，高温井形成激活退火，导致形成剥离区，从而消除了剩余加工步骤的低温限制。

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