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11. 发明申请

US20070054449A1 Methods of forming charge-trapping dielectric layers for semiconductor memory devices 有权
标题翻译：形成用于半导体存储器件的电荷俘获介电层的方法
公开(公告)号：US20070054449A1
公开(公告)日：2007-03-08
申请号：US11209875
申请日：2005-08-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/28211 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.
摘要翻译：在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

12. 发明申请

US20060292800A1 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US20060292800A1
公开(公告)日：2006-12-28
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

13. 发明申请

US20080157184A1 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
标题翻译：操作具有氧化物/氮化物多层绝缘结构的非易失性存储单元的方法
公开(公告)号：US20080157184A1
公开(公告)日：2008-07-03
申请号：US11649348
申请日：2007-01-03
申请人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chin Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Yen-Hao Shih , Tzu-Hsuan Hsu , Shih-Chin Lee , Jung-Yu Hsieh , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/0475 , G11C16/14 , H01L21/28282 , H01L29/4234 , H01L29/513
摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.
摘要翻译：公开了一种通过向栅极施加足以使栅极向电荷存储层进行空穴隧道的正电压来操作存储单元的方法。该方法应用于包括半导体层的存储单元，该半导体层具有设置在半导体层的表面下方并由沟道区分隔开的至少两个源极/漏极区域。存储单元还具有设置在沟道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 设置在电荷存储层上方的上绝缘多层结构。上绝缘多层结构包括下介电层和设置在下介电层上的上氮化物层，并且存储单元具有设置在上绝缘多层结构上方的栅极。

14. 发明申请

US20070108497A1 Low hydrogen concentration charge-trapping layer structures for non-volatile memory and methods of forming the same 有权
标题翻译：用于非挥发性记忆体的低氢浓度电荷捕获层结构及其形成方法
公开(公告)号：US20070108497A1
公开(公告)日：2007-05-17
申请号：US11274781
申请日：2005-11-15
申请人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述衬底之间的界面的氢浓度小于约3×10 6， 11/2/2，以及用于形成这种记忆单元的方法。

15. 发明申请

US20080290397A1 MEMORY CELL AND METHOD FOR MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：存储单元及其制造和操作的方法
公开(公告)号：US20080290397A1
公开(公告)日：2008-11-27
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.
摘要翻译：存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。栅极设置在基板上，并跨接在翅片结构上。电荷捕获结构设置在栅极和鳍结构之间。保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。源极/漏极区域设置在栅极两侧的鳍结构中。

16. 发明授权

US07795088B2 Method for manufacturing memory cell 有权
标题翻译：制造存储单元的方法
公开(公告)号：US07795088B2
公开(公告)日：2010-09-14
申请号：US11753850
申请日：2007-05-25
申请人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
发明人： Tzu-Hsuan Hsu , Ming-Hsiang Hsueh , Yen-Hao Shih , Chia-Wei Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282 , H01L29/42352 , H01L29/66833 , H01L29/792
摘要： A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer. Subsequently, a gate is formed on the substrate and straddles the protection layer, the charge trapping structures and the fin structure. Afterward, source/drain regions are formed in the fin-structure exposed by both sides of the gate.
摘要翻译：提供一种用于制造存储器单元的方法。首先，提供衬底，其中衬底层和材料层已经顺序形成在衬底上。此后，在衬底上形成图案化掩模层。然后，修整图案化的掩模层。随后，通过使用图案化掩模层作为掩模来去除材料层的一部分，衬垫层的一部分和衬底的一部分，以在衬底中限定多个鳍结构。之后，去除图案化的掩模层，并且形成翅片结构中的多个隔离结构。隔离结构的表面比翅片结构的表面低。之后，在基片上形成电荷俘获结构，覆盖翅片结构。成功地，去除一部分电荷捕获结构以暴露材料层。然后，处理过程将材料层转变成保护层。随后，在基板上形成栅极，跨越保护层，电荷捕获结构和鳍结构。之后，源极/漏极区域形成在由栅极两侧暴露的鳍状结构中。

17. 发明授权

US08183618B2 Method for fabricating a charge trapping memory device 有权
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US08183618B2
公开(公告)日：2012-05-22
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

18. 发明申请

US20070293006A1 METHOD FOR FABRICATING A CHARG TRAPPING MEMORY DEVICE 有权
标题翻译：一种用于制作电荷捕捉存储器件的方法
公开(公告)号：US20070293006A1
公开(公告)日：2007-12-20
申请号：US11425160
申请日：2006-06-20
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

19. 发明授权

US07863132B2 Method for fabricating a charge trapping memory device 有权
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US07863132B2
公开(公告)日：2011-01-04
申请号：US11425160
申请日：2006-06-20
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

20. 发明申请

US20110073937A1 Method for Fabricating a Charge Trapping Memory Device 有权
标题翻译：制造电荷俘获存储器件的方法
公开(公告)号：US20110073937A1
公开(公告)日：2011-03-31
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

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