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1. 发明申请

US20070108497A1 Low hydrogen concentration charge-trapping layer structures for non-volatile memory and methods of forming the same 有权
标题翻译：用于非挥发性记忆体的低氢浓度电荷捕获层结构及其形成方法
公开(公告)号：US20070108497A1
公开(公告)日：2007-05-17
申请号：US11274781
申请日：2005-11-15
申请人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述衬底之间的界面的氢浓度小于约3×10 6， 11/2/2，以及用于形成这种记忆单元的方法。

2. 发明申请

US20070054449A1 Methods of forming charge-trapping dielectric layers for semiconductor memory devices 有权
标题翻译：形成用于半导体存储器件的电荷俘获介电层的方法
公开(公告)号：US20070054449A1
公开(公告)日：2007-03-08
申请号：US11209875
申请日：2005-08-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/28211 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/7923
摘要： Methods of forming charge-trapping dielectric layer structures in semiconductor memory devices which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) re-oxidizing the oxide layer; (e) forming a charge-trapping dielectric layer on the oxide layer; and (f) forming an insulating layer on the charge-trapping dielectric layer; as well as methods which comprise: (a) providing a semiconductor substrate; (b) forming an oxide layer on at least a portion of the substrate in a dry atmosphere; (c) forming two or more source/drain regions in the substrate below the oxide layer; (d) forming a charge-trapping dielectric layer on the oxide layer; (e) forming an insulating layer on the charge-trapping dielectric layer; and (f) annealing the insulating layer in an atmosphere having a hydrogen content of less than about 0.01% are described.
摘要翻译：在半导体存储器件中形成电荷俘获电介质层结构的方法包括：（a）提供半导体衬底; （b）在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）氧化氧化层; （e）在所述氧化物层上形成电荷捕获电介质层; 和（f）在电荷俘获电介质层上形成绝缘层; 以及包括：（a）提供半导体衬底的方法; （b）在干燥气氛中在所述基材的至少一部分上形成氧化物层; （c）在氧化物层下面的衬底中形成两个或更多个源极/漏极区域; （d）在氧化物层上形成电荷俘获介电层; （e）在电荷捕获介电层上形成绝缘层; 和（f）在氢含量小于约0.01％的气氛中退火绝缘层。

3. 发明申请

US20070090442A1 Asymmetric floating gate nand flash memory 有权
标题翻译：非对称浮栅nand闪存
公开(公告)号：US20070090442A1
公开(公告)日：2007-04-26
申请号：US11209437
申请日：2005-08-23
申请人： Yen-Hao Shih , Chia-Hua Ho , Hang-Ting Lue , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Chia-Hua Ho , Hang-Ting Lue , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.
摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。因此，浮置栅极下的反相通道可以作为源极/漏极。结果，存储器件不需要浅结或辅助栅。此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

4. 发明申请

US20070201276A1 Dual-gate, non-volatile memory cells, arrays thereof, methods of manufacturing the same and methods of operating the same 有权
标题翻译：双栅极，非易失性存储单元，其阵列，其制造方法及其操作方法
公开(公告)号：US20070201276A1
公开(公告)日：2007-08-30
申请号：US11352788
申请日：2006-02-13
申请人： ChiaHua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang Hsieh
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34 , H01L29/788
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.
摘要翻译：存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

5. 发明申请

US20070069283A1 Method of forming bottom oxide for nitride flash memory 有权
标题翻译：形成氮化物闪存底部氧化物的方法
公开(公告)号：US20070069283A1
公开(公告)日：2007-03-29
申请号：US11235786
申请日：2005-09-27
申请人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Hsieh
发明人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/792 , H01L21/471 , H01L21/8239
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513
摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.
摘要翻译：半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。底部氧化物层可以具有高达5E19cm -3的氢浓度，并且界面陷阱密度高达5E11cm -2EV -1， SUP>。三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

6. 发明申请

US20070241371A1 Memory device and manufacturing method 有权
标题翻译：存储器件及制造方法
公开(公告)号：US20070241371A1
公开(公告)日：2007-10-18
申请号：US11279945
申请日：2006-04-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Hsieh
IPC分类号： H01L29/772 , H01L21/8239
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A memory device includes first and second electrodes separated by an insulating member comprising upwardly and inwardly tapering surfaces connected by a surface segment. A bridge, comprising memory material, such as a phase change material, switchable between electrical property states by the application of energy, is positioned across the surface segment and in contact with the electrodes to define an inter-electrode path defined at least in part by the length of the surface segment. According to a method for making a memory cell device, the tapering surfaces may be created by depositing a dielectric material cap using a high density plasma (HDP) deposition procedure. The electrodes and the dielectric material cap may he planarized to create the surface segment on the dielectric material. At least one of the dielectric material depositing step and the planarizing step may be controlled so that the length of the surface and segment is within a chosen dimensional range, such as between 10 nm and 100 nm.
摘要翻译：存储器件包括由绝缘构件隔开的第一和第二电极，包括由表面段连接的向上和向内的渐缩表面。包括可通过施加能量在电性能状态之间切换的记忆材料（例如相变材料）的桥被定位在表面段上并与电极接触以限定至少部分地由表面段的长度。根据制造存储单元器件的方法，可以通过使用高密度等离子体（HDP）沉积程序沉积介电材料盖而产生锥形表面。电极和电介质材料盖可以被平坦化以在电介质材料上产生表面段。可以控制介电材料沉积步骤和平坦化步骤中的至少一个，使得表面和段的长度在选定的尺寸范围内，例如在10nm和100nm之间。

7. 发明申请

US20070262388A1 Bridge Resistance Random Access Memory Device and Method With A Singular Contact Structure 有权
标题翻译：桥接电阻随机存取存储器件及其具有奇异接触结构的方法
公开(公告)号：US20070262388A1
公开(公告)日：2007-11-15
申请号：US11382422
申请日：2006-05-09
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L23/62 , H01L21/338
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.
摘要翻译：公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电极分离。电阻记忆桥与第一和第二电极的边缘表面接触。接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。位线通过自对准工艺连接到第二电极。

8. 发明申请

US20070173019A1 Programmable Resistive Ram and Manufacturing Method 有权
标题翻译：可编程电阻Ram和制造方法
公开(公告)号：US20070173019A1
公开(公告)日：2007-07-26
申请号：US11426213
申请日：2006-06-23
申请人： ChiaHua Ho , Erh-kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Erh-kun Lai , Kuang Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L27/24 , H01L28/26
摘要： Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.
摘要翻译：可编程电阻RAM单元具有取决于触点尺寸的电阻。公开了具有降低的接触电阻的制造方法和集成电路，其具有减小的尺寸的接触。

9. 发明申请

US20070257300A1 Structures and Methods of a Bistable Resistive Random Access Memory 有权
标题翻译：双稳态电阻随机存取存储器的结构和方法
公开(公告)号：US20070257300A1
公开(公告)日：2007-11-08
申请号：US11381973
申请日：2006-05-05
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Hsieh
IPC分类号： H01L29/788 , H01L21/336 , H01L21/8234 , H01L21/8244
CPC分类号： H01L27/101 , H01L27/24 , H01L45/04 , H01L45/145
摘要： Structures and methods to form a bistable resistive random access memory for reducing the amount of heat dissipation from electrodes by confining a heating region in the memory cell device are described. The heating region is confined in a kernel comprising a programmable resistive memory material that is in contact with an upper programmable resistive memory member and a lower programmable resistive memory member. The lower programmable resistive member has sides that align with sides of a bottom electrode comprising a tungsten plug. The lower programmable resistive member and the bottom electrode function a first conductor so that the amount of heat dissipation from the first conductor is reduced. The upper programmable resistive memory material and a top electrode function as a second conductor so that the amount of heat dissipation from the second conductor is reduced.
摘要翻译：描述了形成双稳态电阻随机存取存储器的结构和方法，用于通过将加热区限制在存储单元装置中来减少从电极散热的量。加热区域被限制在包括与上可编程电阻存储器构件和下可编程电阻存储器构件接触的可编程电阻性存储器材料的内核中。下部可编程电阻构件具有与包括钨插件的底部电极的侧面对准的侧面。下可编程电阻构件和底电极起第一导体的作用，使得来自第一导体的散热量减小。上部可编程电阻性存储器材料和顶部电极用作第二导体，使得来自第二导体的散热量减少。

10. 发明申请

US20070117315A1 Memory cell device and manufacturing method 有权
标题翻译：存储单元器件及其制造方法
公开(公告)号：US20070117315A1
公开(公告)日：2007-05-24
申请号：US11357902
申请日：2006-02-17
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Hsieh
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1691
摘要： A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also disclosed.
摘要翻译：具有可通过施加能量在电性能状态之间切换的记忆材料的存储单元装置包括电极，与电极表面相对的分离层，分离层中的孔，孔中的第二材料限定具有向下和向内逐渐变细的空隙区域。记忆材料位于与电极表面电接触的空隙区域中。第二电极与记忆材料电接触。在第一和第二电极之间的能量通过集中在存储材料内，以便于改变存储材料的电性能状态。记忆材料可以包括相变材料。第二材料可以包括高密度等离子体沉积材料。还公开了一种制造存储单元器件的方法。

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