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11. 发明授权

US07042055B2 Semiconductor device and manufacturing thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US07042055B2
公开(公告)日：2006-05-09
申请号：US10174948
申请日：2002-06-20
申请人： Shinichi Saito , Kazuyoshi Torii , Takahiro Onai , Toshiyuki Mine
发明人： Shinichi Saito , Kazuyoshi Torii , Takahiro Onai , Toshiyuki Mine
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62
CPC分类号： H01L29/4983 , H01L21/28017 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L29/4916 , H01L29/4925 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.
摘要翻译：在小型场效应晶体管中，栅介质膜与栅电极之间的界面的粗糙度被控制在原子尺度上。栅电介质膜的厚度变化降低，由此制造具有高迁移率的场效应晶体管。场效应晶体管的迁移率的增加不仅可以在使用常规的SiO 2热氧化膜作为栅极电介质膜的情况下实现，而且在使用高介电材料的情况下也可以实现用于栅介质膜。

12. 发明授权

US06894334B2 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06894334B2
公开(公告)日：2005-05-17
申请号：US10376329
申请日：2003-03-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

13. 发明申请

US20050045970A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050045970A1
公开(公告)日：2005-03-03
申请号：US10913551
申请日：2004-08-09
申请人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
发明人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
IPC分类号： C23C16/42 , H01L21/28 , H01L21/316 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
摘要翻译：硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。高k膜包含过渡金属，铝，硅和氧。高k膜中的硅的浓度高于与SiO 2膜的界面附近和与栅电极的界面附近的过渡金属和铝的浓度。此外，优选的是，至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着与这些界面的距离而逐渐减小，并且变得最低在高k电影的中心部分。

14. 发明授权

US06548847B2 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM 失效
标题翻译：具有通过连接孔暴露的第一布线的半导体集成电路器件，连接孔中的过渡金属膜和铝导线之间的过渡金属膜以及铝导线和过渡金属膜之间的过渡金属氮化物膜
公开(公告)号：US06548847B2
公开(公告)日：2003-04-15
申请号：US09899921
申请日：2001-07-09
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

15. 发明授权

US08344604B2 Spark plug for internal combustion engine 有权
标题翻译：内燃机火花塞
公开(公告)号：US08344604B2
公开(公告)日：2013-01-01
申请号：US12743092
申请日：2008-11-13
申请人： Kazuyoshi Torii , Naomichi Miyashita , Mamoru Musasa , Akira Suzuki , Tomoo Tanaka , Osamu Yoshimoto
发明人： Kazuyoshi Torii , Naomichi Miyashita , Mamoru Musasa , Akira Suzuki , Tomoo Tanaka , Osamu Yoshimoto
IPC分类号： H01T13/20 , H01T21/02
CPC分类号： H01T13/39
摘要： A precious metal tip on the side of a ground electrode is indirectly joined to the front end portion of the ground electrode via a mounting part interposed therebetween. The mounting part includes a base part and a protruding part. First, in the state where the precious metal tip is in contact with the protruding part, laser welding or the like is performed thereon to form a fused part and obtain a complex, and the base part is joined to a flat surface of the ground electrode by resistance welding. The grain size of grains of the mounting part in the vicinity of the of the fused part is greater than the grain size of the grain size of the grains thereof in the vicinity of the ground electrode, and the grain size of the grains of the flange part of the mounting part is smaller than the grain size of the grains of the protruding part.
摘要翻译：接地电极侧的贵金属端头经由插入其间的安装部分间接地接合到接地电极的前端部。安装部分包括基部和突出部。首先，在贵金属端头与突出部接触的状态下，进行激光焊接等，形成熔融部，得到复合体，基部与接地电极的平坦面接合通过电阻焊接。熔融部附近的安装部的晶粒尺寸大于接地电极附近的晶粒的晶粒尺寸，凸缘的晶粒的粒径安装部的一部分小于突出部的晶粒的粒径。

16. 发明申请

US20110163653A1 SPARK PLUG 有权
标题翻译： SPARK插头
公开(公告)号：US20110163653A1
公开(公告)日：2011-07-07
申请号：US13062571
申请日：2009-09-09
申请人： Kazuyoshi Torii , Tomoo Tanaka , Akira Suzuki , Mamoru Musasa , Naomichi Miyashita , Osamu Yoshimoto
发明人： Kazuyoshi Torii , Tomoo Tanaka , Akira Suzuki , Mamoru Musasa , Naomichi Miyashita , Osamu Yoshimoto
IPC分类号： H01T13/20
CPC分类号： H01T13/39 , B23K35/322 , C22C5/04 , C22C19/058
摘要： A spark plug includes a cylindrical metal shell; a cylindrical insulator that is held in the metal shell; a center electrode; and a ground electrode that comprises a ground electrode main body part and a noble metal tip, a spark discharge gap being formed between the leading end of the center electrode and the noble metal tip wherein at least a portion of the ground electrode main body part, to which the noble metal tip is joined, is made of Ni alloy containing 12 to 35 mass % of Cr, 7 mass % or less of Fe, 0.5 to 5 mass % of Al, 0.3 to 5 mass % of Si and 50 mass % or more of the balance, and wherein the joined portion and the noble metal tip are joined by laser welding or electron beam welding.
摘要翻译：火花塞包括圆柱形金属壳; 保持在金属外壳中的圆柱形绝缘体; 中心电极; 以及接地电极，其包括接地电极主体部分和贵金属电极头，在所述中心电极的前端与所述贵金属电极头之间形成火花放电间隙，其中所述接地电极主体部分的至少一部分，贵金属电极头接合的Ni合金由含有12〜35质量％的Cr，7质量％以下的Fe，0.5〜5质量％的Al，0.3〜5质量％的Si和50质量％的Ni合金构成，或更多的平衡，并且其中通过激光焊接或电子束焊接将接合部分和贵金属电极头接合。

17. 发明授权

US07630043B2 Liquid display device and fabrication method thereof 有权
标题翻译：液体显示装置及其制造方法
公开(公告)号：US07630043B2
公开(公告)日：2009-12-08
申请号：US11777853
申请日：2007-07-13
申请人： Takashi Hattori , Daisuke Sonoda , Daisuke Ryuzaki , Kazuyoshi Torii
发明人： Takashi Hattori , Daisuke Sonoda , Daisuke Ryuzaki , Kazuyoshi Torii
IPC分类号： G02F1/1333
CPC分类号： G02F1/136213 , G02F1/134363 , G02F2001/133357 , G02F2202/38 , G02F2202/42
摘要： A liquid crystal display improved with the opening ratio and increased for the storage capacitance, in which a gate insulating film, a gate electrode, an interlayer insulating film, an image line and a source electrode are stacked in this order formed in the layer above an active device formed to a first substrate, the interlayer insulating film is formed with a coatable transparent insulating film having a specific dielectric constant of 4.0 or higher at least containing high dielectric fine particle or sol-gel, a first through hole is formed in the gate insulating film, a second through hole is formed to the interlayer insulating film in the inside of the first through hole, the source electrode is electrically connected with the active device by way of the second through hole, and the storage capacitance is constituted by the gate electrode, the image line, the source electrode, and the interlayer insulating film.
摘要翻译：液晶显示器的开口率提高，并且对于其中栅极绝缘膜，栅极电极，层间绝缘膜，图像线和源极电极以此顺序堆叠形成在上面的层中的存储电容而增加有源器件形成于第一衬底上，层间绝缘膜由至少包含高电介质微粒或溶胶 - 凝胶的比介电常数为4.0以上的可涂覆透明绝缘膜形成，在栅极中形成第一通孔绝缘膜，在第一通孔的内部形成有层间绝缘膜的第二贯通孔，源电极通过第二通孔与有源器件电连接，保持电容由栅极构成电极，图像线，源电极和层间绝缘膜。

18. 发明申请

US20070216275A1 SPARK PLUG FOR USE IN AN INTERNAL-COMBUSTION ENGINE 有权
标题翻译：火花塞用于内燃机
公开(公告)号：US20070216275A1
公开(公告)日：2007-09-20
申请号：US11687828
申请日：2007-03-19
申请人： Kazuyoshi Torii , Kazumasa Yoshida , Wataru Matsutani
发明人： Kazuyoshi Torii , Kazumasa Yoshida , Wataru Matsutani
IPC分类号： H01T13/20
CPC分类号： H01T21/02 , H01T13/20 , H01T13/36 , H01T13/39
摘要： A spark plug 100 comprised of a metal shell 1, an insulator 2, a center electrode 3 and a ground electrode 4. A rear-end face of the ground electrode 4 is welded to a front-end face of the metal shell 1, and a bent portion 5 located at the intermediated position in the longitudinal direction is bent toward the center of the spark plug 100. The ground electrode 4 assumes a circular-shape with a diameter of 2 mm or less whereby an inflow of an air-fuel mixture is not disturbed even when the air-fuel mixture directly flows into a back face of the ground electrode 4. The ground electrode 4 is comprised of an outer layer 4A made of a nickel alloy and an inner layer 4B made of pure copper with an excellent thermal conductivity, in which a ratio of a cross-sectional area of the inner layer 4B to the entire cross-sectional area of the ground electrode 4 is 10% or more to 35% or less. Thus, the spark plug 100 which is excellent in heat sinking ability and can prevent a spring back phenomenon due to a difference in a coefficient of thermal expansion.
摘要翻译：由金属壳1，绝缘体2，中心电极3和接地电极4构成的火花塞100.接地电极4的后端面焊接在金属壳1的前端面上，位于中间位置的弯曲部分5朝向火花塞100的中心弯曲。接地电极4呈直径为2mm或更小的圆形，由此空气 - 燃料混合物即使当空气 - 燃料混合物直接流入接地电极4的背面时也不会受到干扰。接地电极4包括由镍合金制成的外层4A和由纯铜制成的内层4B，内层4B的截面积与接地电极4的整个横截面积的比率为10％以上35％以下的良好的导热性。因此，具有散热能力优异且能够防止由于热膨胀系数的差异引起的弹回现象的火花塞100。

19. 发明申请

US20070092661A1 Liquid crystal display device and dielectric film usable in the liquid crystal display device 有权
标题翻译：可用于液晶显示装置的液晶显示装置和电介质膜
公开(公告)号：US20070092661A1
公开(公告)日：2007-04-26
申请号：US11583882
申请日：2006-10-20
申请人： Daisuke Ryuzaki , Kazuyoshi Torii , Mutsuko Hatano , Daisuke Sonoda , Toshiki Kaneko
发明人： Daisuke Ryuzaki , Kazuyoshi Torii , Mutsuko Hatano , Daisuke Sonoda , Toshiki Kaneko
IPC分类号： C09K19/00
CPC分类号： G02F1/1362 , G02F1/133345 , G02F2202/02 , H01L21/02126 , H01L21/02222 , H01L21/02282 , H01L21/3122 , H01L21/31633 , H01L21/3185 , Y10T428/10
摘要： The present invention provides a liquid crystal display device with high image visibility at low power consumption and produced at low cost by using an interlayer dielectric film, which has low dielectric constant, high heat-resistant property, high optical transmissivity, high film thickness and high flattening property produced at low cost. An organic siloxane dielectric film is used as an interlayer dielectric film of the liquid crystal display device. A ratio of nitrogen content to silicon content (Ni content/Si content) in the interlayer dielectric film is controlled to 0.04 or more in the element ratio. The limiting film thickness to suppress and limit the cracking caused by the thickening of the interlayer dielectric film is set to 1.5 μm or more.
摘要翻译：本发明提供一种低功耗的高图像可见度的液晶显示装置，通过使用具有低介电常数，高耐热性，高透光率，高膜厚和高的层间绝缘膜以低成本生产的液晶显示装置以低成本生产的扁平性。使用有机硅氧烷介电膜作为液晶显示装置的层间电介质膜。层间电介质膜中的氮含量与硅含量（Ni含量/ Si含量）的比例以元素比控制在0.04以上。抑制和限制由层间电介质膜的增厚引起的裂纹的限制膜厚设定为1.5μm以上。

20. 发明申请

US20060214198A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214198A1
公开(公告)日：2006-09-28
申请号：US11385885
申请日：2006-03-22
申请人： Takeo Matsuki , Kazuyoshi Torii
发明人： Takeo Matsuki , Kazuyoshi Torii
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/0217 , H01L21/02271 , H01L21/28176 , H01L21/28185 , H01L21/3185 , H01L21/76829 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： An object of this invention is to prevent the NBTI degradation which may occur following the recent progress in miniaturization of the semiconductor device. By using a silicon nitride film, in which a concentration of Si—H bonds is not greater than 1×1021 cm−3, at least for a liner film or a second sidewall insulating film, the NBTI lifetime of the p-type MOS FET can be improved to be 1×109 seconds, which secures sufficient lifetime for the semiconductor integrated circuit device.
摘要翻译：本发明的目的是防止在半导体器件的最小化的最新进展之后可能发生的NBTI劣化。通过使用其中Si-H键的浓度不大于1×10 -2 cm -3的氮化硅膜，至少对于衬垫膜或第二侧壁绝缘膜，p型MOS FET的NBTI寿命可以提高到1×10 9秒，这为半导体集成电路器件确保了足够的寿命。

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