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11. 发明授权

US07714608B1 Temperature-independent, linear on-chip termination resistance 有权
标题翻译：温度独立，线性片上终端电阻
公开(公告)号：US07714608B1
公开(公告)日：2010-05-11
申请号：US12370039
申请日：2009-02-12
申请人： Mou C. Lin , William B. Andrews , John A. Schadt
发明人： Mou C. Lin , William B. Andrews , John A. Schadt
IPC分类号： H03K17/16
CPC分类号： H04L25/0298 , H01L28/20
摘要： In one embodiment, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. A sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.
摘要翻译：在一个实施例中，诸如FPGA的集成电路具有一个或多个可编程端接方案，每个可编程端接方案具有并联连接的多个电阻端接支路，以及设计成控制处理，电压和温度的每个端接方案的校准电路（PVT）变化。校准电路中的感测元件和每个端接方案中的每个电阻支路具有与非硅化聚（NSP）电阻器串联连接的基于晶体管的传输栅极。每个NSP电阻器的负温度系数抵消相应传输门的电阻率的正温度系数，以提供与温度无关的感测元件和温度独立的端接脚。感测元件和终端支路的温度独立性和恒定IV特性使得单个校准电路能够同时控制在不同终端电压电平下工作的多个终端方案。

12. 发明授权

US07443192B1 Output buffer with digital slew control 有权
标题翻译：输出缓冲器，带数字转换控制
公开(公告)号：US07443192B1
公开(公告)日：2008-10-28
申请号：US11643288
申请日：2006-12-21
申请人： William B. Andrews , Mou C. Lin , John A. Schadt
发明人： William B. Andrews , Mou C. Lin , John A. Schadt
IPC分类号： H03K19/003
CPC分类号： H03K19/00369
摘要： An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.
摘要翻译：一种改进的输出缓冲器，具有数字输出摆幅控制和补偿制造工艺变化。输出回转是通过将数字驱动信号排列成并联的输出晶体管来实现的。在一个实施例中，预驱动器通过使用串行数字逻辑门的传播延迟来排序驱动信号，以减少电源下降和/或地面反弹。输出晶体管基本上同时截止，以避免在输出缓冲器改变状态时不期望的电源DC电流流动。可编程地配置可以在任何给定时间导通的并联晶体管的数量允许用户补偿制造工艺变化并确定缓冲器的输出阻抗/驱动能力。

13. 发明授权

US07009433B2 Digitally controlled delay cells 有权
标题翻译：数字控制延时单元
公开(公告)号：US07009433B2
公开(公告)日：2006-03-07
申请号：US10447451
申请日：2003-05-28
申请人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
发明人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0805
摘要： Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
摘要翻译：本文公开了在集成电路中实现信号延迟的系统和方法。例如，根据本发明的实施例，主延迟电路可以数字地控制一个或多个从延迟单元以支持可编程逻辑器件的各种应用。

14. 发明授权

US6028447A FPGA having predictable open-drain drive mode 失效
标题翻译： FPGA具有可预测的开漏驱动模式
公开(公告)号：US6028447A
公开(公告)日：2000-02-22
申请号：US899428
申请日：1997-07-24
申请人： William B. Andrews , James F. Hoff , Satwant Singh
发明人： William B. Andrews , James F. Hoff , Satwant Singh
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： H03K19/1736
摘要： A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.
摘要翻译：具有至少一个可编程单元（例如，输入/输出（I / O）单元）的现场可编程门阵列（FPGA）具有输出节点电路（例如，pad电路），其中输出数据信号和三状态信号被施加到驱动输出节点电路中的输出缓冲器的三态端口的多路复用器。该配置使得输出节点电路能够以不需要依赖于FPGA的通用路由资源的快速，可预测的方式配置为开漏驱动模式操作。

15. 发明授权

US07844243B1 Receiver for differential and reference voltage signaling with programmable common mode 有权
标题翻译：差分和参考电压信号接收器，具有可编程通用模式
公开(公告)号：US07844243B1
公开(公告)日：2010-11-30
申请号：US12402751
申请日：2009-03-12
申请人： William B. Andrews , John Schadt
发明人： William B. Andrews , John Schadt
IPC分类号： H04B1/28 , H04B1/16
CPC分类号： H04L25/0272 , H04L25/0264 , H04L25/0294
摘要： In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel nodes between a pad and the mux output and (ii) to receive a control signal at its gate node. Control circuitry for the p-type transistor implements a threshold reduction filter that ensures that a maximum voltage level at the mux output is at least a threshold below the mux's power supply voltage. Based on first and second input signals, the first receiver circuit generates first and second intermediate signals, and the second receiver circuit generates third and fourth intermediate signals. The mixer circuit combines the intermediate signals to generate first and second output signals, wherein the first and second receiver circuits effectively operate over different ranges of common-mode voltages.
摘要翻译：在本发明的一个实施例中，接收器具有两个多路复用电路，两个接收器电路和混频器。多路复用器为接收机电路选择第一和第二输入信号。每个多路复用器中的传输门中的p型晶体管在其沟道节点处连接（i）在焊盘和多路复用器输出之间，以及（ii）在其栅极节点处接收控制信号。用于p型晶体管的控制电路实现阈值滤波器，其确保多路复用器输出处的最大电压电平至少低于多路复用器电源电压的阈值。基于第一和第二输入信号，第一接收器电路产生第一和第二中间信号，第二接收器电路产生第三和第四中间信号。混频器电路组合中间信号以产生第一和第二输出信号，其中第一和第二接收器电路有效地在不同的共模电压范围上工作。

16. 发明授权

US07605609B1 Programmable level shifter 有权
标题翻译：可编程电平转换器
公开(公告)号：US07605609B1
公开(公告)日：2009-10-20
申请号：US11957598
申请日：2007-12-17
申请人： William B. Andrews , Mou C. Lin , John Schadt
发明人： William B. Andrews , Mou C. Lin , John Schadt
IPC分类号： H03K19/0175
CPC分类号： H03K3/356165
摘要： In one embodiment of the invention, a programmable level shifter can be selectively configured to operate in either a high-speed mode or a low-power mode. In both modes, the level shifter converts an input signal in one power supply domain into an output signal in another power supply domain. In the high-speed mode, p-type devices are configured as a current-mirror amplifier that provides the level shifter with relatively fast switching speed. In the low-power mode, the same p-type devices are configured as a cross-coupled latch that provides the level shifter with relatively low power consumption. Selectively enabled n-type devices provide the low-power mode with larger effective n-type devices to flip the cross-coupled latch formed by the p-type devices in the low-power mode.
摘要翻译：在本发明的一个实施例中，可编程电平转换器可被选择性地配置为以高速模式或低功率模式工作。在两种模式中，电平移位器将一个电源域中的输入信号转换为另一个电源域中的输出信号。在高速模式中，p型器件被配置为电流镜放大器，为电平转换器提供相对较快的开关速度。在低功耗模式中，相同的p型器件被配置为交叉耦合的锁存器，其为电平移位器提供相对较低的功耗。选择性使能的n型器件提供具有较大有效n型器件的低功耗模式，以在低功耗模式下翻转由p型器件形成的交叉耦合锁存器。

17. 发明授权

US07586325B1 Integrated circuit having independent voltage and process/temperature control 有权
标题翻译：具有独立电压和工艺/温度控制的集成电路
公开(公告)号：US07586325B1
公开(公告)日：2009-09-08
申请号：US11949130
申请日：2007-12-03
申请人： William B. Andrews , Mou C. Lin , John Schadt
发明人： William B. Andrews , Mou C. Lin , John Schadt
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00369 , H03K17/14 , H03K19/17748 , H03K19/1778
摘要： In one embodiment, an integrated circuit has configurable application circuitry that operates at any one of multiple available power supply voltages. PT-control circuitry, operating at a PT reference voltage, generates a PT-control signal indicative of variations in process and temperature. Application-control circuitry controls the configuration of the application circuitry based on the selected power supply voltage for the application circuitry and the PT-control signal, where the selected power supply voltage is independent of the PT reference voltage. In one implementation, the application circuitry is an output driver having source and sink driver blocks, where driver-control circuitry controls the configuration of the source driver block based on the selected output-driver power supply voltage, a source PT-control signal, and a selected drive strength, while controlling the configuration of the sink driver block based on the selected output-driver power supply voltage, a sink PT-control signal, and a selected drive strength.
摘要翻译：在一个实施例中，集成电路具有可操作的多个可用电源电压中的任何一个的可配置应用电路。以PT参考电压工作的PT控制电路产生指示过程和温度变化的PT控制信号。应用控制电路基于用于应用电路和PT控制信号的所选择的电源电压控制应用电路的配置，其中所选择的电源电压独立于PT参考电压。在一个实现中，应用电路是具有源和接收器驱动器块的输出驱动器，其中驱动器控制电路基于所选择的输出驱动器电源电压来控制源极驱动器模块的配置，源PT控制信号和选择的驱动强度，同时基于所选择的输出驱动器电源电压，信宿PT控制信号和选择的驱动强度来控制接收器驱动器块的配置。

18. 发明授权

US06486705B2 Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units 有权
标题翻译：现场可编程门阵列（FPGA）或现场可编程系统芯片（FPSC）中的信号分配方案，包括循环窃取单元
公开(公告)号：US06486705B2
公开(公告)日：2002-11-26
申请号：US09864276
申请日：2001-05-25
申请人： William B. Andrews , Alfred E. Dunlop , John P. Fishburn , Harold N. Scholz
发明人： William B. Andrews , Alfred E. Dunlop , John P. Fishburn , Harold N. Scholz
IPC分类号： H03K1900
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.
摘要翻译：在诸如FPGA或FPSC的可编程设备的路由中引入了分数循环窃取单元，以增加由特定时钟路由引起的系统性能。所公开的分数循环窃取单元使得在各个分配汇之间和/或在串联的逻辑路径之间的给定量的时钟偏移。每个延迟元件从后续电路“窃取”时钟周期（或许一个或多个完整的时钟周期）的一部分，以提供更可靠的逻辑功能，并避免对整体额外的时钟周期的需要这些分数周期窃取元件在分布的接收器处提供信号偏移调整，没有额外的路由拥塞费用。公开的周期窃取延迟元件是可编程的，并且使得各个分配汇之间的时钟偏移。

19. 发明授权

US07547995B1 Dynamic over-voltage protection scheme for interface circuitry 有权
标题翻译：接口电路的动态过压保护方案
公开(公告)号：US07547995B1
公开(公告)日：2009-06-16
申请号：US11345713
申请日：2006-02-02
申请人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
发明人： William B. Andrews , Larry R Fenstermaker , John A. Schadt , Mou C. Lin
IPC分类号： H01H9/54
CPC分类号： H03K19/00315 , Y10T307/944
摘要： In one embodiment of the invention, an integrated device has interface circuitry that includes a dynamic monitor that monitors the relative potential between (at least) two different power supplies to enable the device to react to over-voltage conditions such that appropriate selections can be made for which power supplies are selected for different components in the interface circuitry, such as output drivers and input receivers. The dynamic monitor enables over-voltage protection to be automatically implemented before the device has been configured, such as during the device's power-on state.
摘要翻译：在本发明的一个实施例中，集成器件具有接口电路，该接口电路包括监视（至少）两个不同电源之间的相对电位的动态监视器，以使器件能够对过电压条件作出反应，从而可以进行适当的选择为接口电路中的不同组件选择哪个电源，例如输出驱动器和输入接收器。动态监视器可以在设备配置之前自动实现过电压保护，例如在设备通电状态期间。

20. 发明申请

US20080029932A1 MOLDING MACHINE WITH PLATEN-ATTACHED HOT RUNNER MANIFOLD 审中-公开
标题翻译：模具机与附加的热流道管道
公开(公告)号：US20080029932A1
公开(公告)日：2008-02-07
申请号：US11830400
申请日：2007-07-30
申请人： John R. Zietlow , William B. Andrews
发明人： John R. Zietlow , William B. Andrews
IPC分类号： B29C45/22
CPC分类号： B29C45/2701 , B29C2045/2762 , B29C2045/2796
摘要： An apparatus includes an injection molding machine, a hot runner apparatus attached to the molding machine, and a mold defining a part cavity. The mold is attached to the molding machine and operably engages the hot runner apparatus. The hot runner apparatus has secondary nozzles that engage respective sprue assemblies on the mold for communicating melted plastic material to the mold cavity. Each sprue assembly includes a movably mounted sprue and a stress-reducing mechanism with spring washers that support the sprue to provide sufficient force to eliminate leaking at abutting contact surfaces against the secondary nozzles, but that allow limited movement of the sprue to reduce excessive stress focused on the respective sprues. Since the stress-reducing mechanism is located in the mold, each stress-reducing mechanism can be tailored to the particular needs of that particular mold and the particular melted material being processed.
摘要翻译：一种装置包括注射成型机，附着在成型机上的热流道装置和限定部分空腔的模具。模具附接到成型机并可操作地接合热流道装置。热流道装置具有二次喷嘴，该二次喷嘴与模具上的相应的浇口组件接合，用于将熔融的塑料材料连通到模腔。每个浇道组件包括可移动地安装的浇口和具有弹簧垫圈的减压机构，弹簧垫圈支撑浇道以提供足够的力以消除邻接二次喷嘴的邻接接触面处的泄漏，但是允许浇道的有限运动以减少过度的应力集中在各自的浇道上。由于应力减小机构位于模具中，每个减压机构可以根据特定模具和被加工的特定熔化材料的特定需要进行调整。

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